Albert Jan Huitsing

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Nijmegen, NL

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Patents Grantslast 30 patents

Information Patent Grant
Local interconnect layer enhanced ESD in a bipolar-CMOS-DMOS
- Patent number 9,653,447
- Issue date May 16, 2017
- NXP B.V.
- Albert Jan Huitsing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bias-insensitive trigger circuit for bigFET ESD supply protection
- Patent number 9,153,958
- Issue date Oct 6, 2015
- NXP B.V.
- Gijs de Raad
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Secondary ESD circuit
- Patent number 8,654,488
- Issue date Feb 18, 2014
- NXP B.V.
- Albert Jan Huitsing
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Fail-safe method and circuit
- Patent number 7,265,574
- Issue date Sep 4, 2007
- NXP, B.V.
- Albert Jan Huitsing
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LIL ENHANCED ESD-PNP IN A BCD
- Publication number 20160086934
- Publication date Mar 24, 2016
- NXP. B.V.
- Albert Jan Huitsing
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS-INSENSITIVE TRIGGER CIRCUIT FOR BIGFET ESD SUPPLY PROTECTION
- Publication number 20150049403
- Publication date Feb 19, 2015
- NXP B.V.
- Gijs de Raad
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Secondary ESD Circuit
- Publication number 20120008243
- Publication date Jan 12, 2012
- Albert Jan Huitsing
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
TRANSFORMATION OF AN INPUT SIGNAL INTO A LOGICAL OUTPUT VOLTAGE LEV...
- Publication number 20090009217
- Publication date Jan 8, 2009
- NXP B.V.
- Albert Jan Huitsing
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fail-safe method and circuit
- Publication number 20050285632
- Publication date Dec 29, 2005
- Albert Jan Huitsing
- H03 - BASIC ELECTRONIC CIRCUITRY