Albert Ma

Person

Belmont, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit and method for translation lookaside buffer (TLB) implement...
- Patent number 12,032,488
- Issue date Jul 9, 2024
- MARVELL ASIA PTE. LTD.
- Albert Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for large memory transaction (LMT) stores
- Patent number 11,960,727
- Issue date Apr 16, 2024
- MARVELL ASIA PTE. LTD.
- Aadeetya Shreedhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for mapping memory addresses to locations in set-...
- Patent number 11,620,225
- Issue date Apr 4, 2023
- MARVELL ASIA PTE. LTD.
- Albert Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration cache for the ARM SMMUv3
- Patent number 11,474,953
- Issue date Oct 18, 2022
- Marvell Asia Pte, Ltd.
- Manan Salvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for mapping memory addresses to locations in set-...
- Patent number 11,416,405
- Issue date Aug 16, 2022
- MARVELL ASIA PTE. LTD.
- Albert Ma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction ordering for in-progress operations
- Patent number 10,339,054
- Issue date Jul 2, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing resources in a multi-context computing system
- Patent number 10,303,514
- Issue date May 28, 2019
- Cavium, LLC
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for interfacing a pipeline with two or more interfaces in...
- Patent number 10,078,601
- Issue date Sep 18, 2018
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction ordering for in-progress operations
- Patent number 9,910,776
- Issue date Mar 6, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributing resource requests in a computing system
- Patent number 9,678,717
- Issue date Jun 13, 2017
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Caching TLB translations using a unified page table walker cache
- Patent number 9,405,702
- Issue date Aug 2, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Configuration Cache For The ARM SMMUv3
- Publication number 20200117613
- Publication date Apr 16, 2020
- Marvell World Trade Ltd.
- Manan Salvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ORDERING FOR IN-PROGRESS OPERATIONS
- Publication number 20180165197
- Publication date Jun 14, 2018
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ORDERING FOR IN-PROGRESS OPERATIONS
- Publication number 20160140043
- Publication date May 19, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE MEMORY MANAGEMENT UNITS
- Publication number 20160140059
- Publication date May 19, 2016
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING RESOURCES IN A MULTI-CONTEXT COMPUTING SYSTEM
- Publication number 20160139950
- Publication date May 19, 2016
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTING RESOURCE REQUESTS IN A COMPUTING SYSTEM
- Publication number 20160139883
- Publication date May 19, 2016
- Cavium, Inc.
- Wilson P. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHING TLB TRANSLATIONS USING A UNIFIED PAGE TABLE WALKER CACHE
- Publication number 20160140048
- Publication date May 19, 2016
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Circuit and method for translation lookaside buffer (TLB) implement...

System and method for large memory transaction (LMT) stores

System and method for mapping memory addresses to locations in set-...

Configuration cache for the ARM SMMUv3

System and method for mapping memory addresses to locations in set-...

Instruction ordering for in-progress operations

Sharing resources in a multi-context computing system

Approach for interfacing a pipeline with two or more interfaces in...

Instruction ordering for in-progress operations

Distributing resource requests in a computing system

Caching TLB translations using a unified page table walker cache

Patents Applicationslast 30 patents

Configuration Cache For The ARM SMMUv3

INSTRUCTION ORDERING FOR IN-PROGRESS OPERATIONS

INSTRUCTION ORDERING FOR IN-PROGRESS OPERATIONS

MULTIPLE MEMORY MANAGEMENT UNITS

SHARING RESOURCES IN A MULTI-CONTEXT COMPUTING SYSTEM

DISTRIBUTING RESOURCE REQUESTS IN A COMPUTING SYSTEM

CACHING TLB TRANSLATIONS USING A UNIFIED PAGE TABLE WALKER CACHE