Albert Shih-Huai Lin

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Mountain View, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit chip testing interface with reduced signal wires
- Patent number 11,860,228
- Issue date Jan 2, 2024
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid synchronous and asynchronous control for scan-based testing
- Patent number 11,755,804
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing memory elements using an internal testing interface
- Patent number 11,500,017
- Issue date Nov 15, 2022
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit architecture for expanded design for testability functionality
- Patent number 11,263,377
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DFxNoC - A MULTI-PROTOCOL, MULTI-CAST, AND MULTI-ROOT NETWORK-ON-CH...
- Publication number 20240356544
- Publication date Oct 24, 2024
- Xilinx, Inc.
- Rambabu NERUKONDA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
- Publication number 20230366929
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Albert Shih-Huai LIN
- G01 - MEASURING TESTING
Information Patent Application
HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING
- Publication number 20230205959
- Publication date Jun 29, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING