Alexander FISH

Person

Tel-Mond, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Secured memory
- Patent number 11,586,778
- Issue date Feb 21, 2023
- Bar-Ilan University
- Robert Giterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information redistribution to reduce side channel leakage
- Patent number 11,321,460
- Issue date May 3, 2022
- Bar-Ilan University
- Alexander Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fin-FET gain cells
- Patent number 11,127,455
- Issue date Sep 21, 2021
- Bar-Ilan University
- Adam Teman
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-asynchronous digital circuit design
- Patent number 11,023,632
- Issue date Jun 1, 2021
- Bar-IIan University
- Itamar Levi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complementary dual-modular redundancy memory cell
- Patent number 10,991,421
- Issue date Apr 27, 2021
- Bar-Ilan University
- Robert Giterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Randomized logic against side channel attacks
- Patent number 10,951,391
- Issue date Mar 16, 2021
- Bar-Ilan University
- Moshe Avital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-asynchronous digital circuit design
- Patent number 10,572,619
- Issue date Feb 25, 2020
- Bar-Ilan University
- Itamar Levi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data-dependent delay circuits
- Patent number 10,521,530
- Issue date Dec 31, 2019
- Bar-Ilan University
- Itamar Levi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-density memory macro
- Patent number 10,497,410
- Issue date Dec 3, 2019
- Mellanox Technologies, Ltd.
- Elad Mentovich
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-topology logic gates
- Patent number 10,169,617
- Issue date Jan 1, 2019
- Bar-Ilan University
- Alexander Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transistor gain cell with feedback
- Patent number 10,002,660
- Issue date Jun 19, 2018
- Bar-Ilan University
- Robert Giterman
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistor gain cell with feedback
- Patent number 9,691,445
- Issue date Jun 27, 2017
- Bar-Ilan University
- Robert Giterman
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode logic circuits
- Patent number 9,430,598
- Issue date Aug 30, 2016
- Bar-Ilan University
- Alexander Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for dual-mode logic
- Patent number 8,901,965
- Issue date Dec 2, 2014
- Ben-Gurion University of the Negev Research & Development Authority
- Alexander Fish
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra low power memory cell with a supply feedback loop configured...
- Patent number 8,773,895
- Issue date Jul 8, 2014
- Ben-Gurion University of the Negev Research & Development Authority
- Adam Teman
- G11 - INFORMATION STORAGE
Information Patent Grant
Ultra low power SRAM cell circuit with a supply feedback loop for n...
- Patent number 8,531,873
- Issue date Sep 10, 2013
- Ben-Gurion University of the Negev Research and Development Authority
- Adam Teman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MITIGATION OF DROOP TIMING ERRORS INCLUDING A DROOP DETE...
- Publication number 20220166431
- Publication date May 26, 2022
- Bar Ilan University
- Joseph Shor
- G01 - MEASURING TESTING
Information Patent Application
INFORMATION REDISTRIBUTION TO REDUCE SIDE CHANNEL LEAKAGE
- Publication number 20210200865
- Publication date Jul 1, 2021
- Bar-Ilan University
- Alexander FISH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIN-FET GAIN CELLS
- Publication number 20210166751
- Publication date Jun 3, 2021
- Bar-Ilan University
- Adam TEMAN
- G11 - INFORMATION STORAGE
Information Patent Application
SECURED MEMORY
- Publication number 20200372186
- Publication date Nov 26, 2020
- Bar-Ilan University
- Robert GITERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-ASYNCHRONOUS DIGITAL CIRCUIT DESIGN
- Publication number 20200082031
- Publication date Mar 12, 2020
- BAR-LLAN UNIVERSITY
- Itamar LEVI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLEMENTARY DUAL-MODULAR REDUNDANCY MEMORY CELL
- Publication number 20190295633
- Publication date Sep 26, 2019
- BAR-LLAN UNIVERSITY
- Robert GITERMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO- ASYNCHRONOUS DIGITAL CIRCUIT DESIGN
- Publication number 20190220554
- Publication date Jul 18, 2019
- BAR-LLAN UNIVERSITY
- Itamar LEVI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPACT BIT GENERATOR
- Publication number 20190187957
- Publication date Jun 20, 2019
- Bar-Ilan University
- Moshe Avital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-density memory macro
- Publication number 20190074040
- Publication date Mar 7, 2019
- MELLANOX TECHNOLOGIES, LTD.
- Elad Mentovich
- G11 - INFORMATION STORAGE
Information Patent Application
RANDOMIZED LOGIC AGAINST SIDE CHANNEL ATTACKS
- Publication number 20190028263
- Publication date Jan 24, 2019
- Bar-Ilan University
- Moshe AVITAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA-DEPENDENT DELAY CIRCUITS
- Publication number 20180032655
- Publication date Feb 1, 2018
- Bar-Ilan University
- Itamar LEVI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR GAIN CELL WITH FEEDBACK
- Publication number 20170294221
- Publication date Oct 12, 2017
- Bar-Ilan University
- Robert GITERMAN
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-TOPOLOGY LOGIC GATES
- Publication number 20170169220
- Publication date Jun 15, 2017
- Bar-Ilan University
- Alexander FISH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR GAIN CELL WITH FEEDBACK
- Publication number 20170062024
- Publication date Mar 2, 2017
- Bar-Ilan University
- Robert GITERMAN
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN OF DUAL MODE LOGIC CIRCUITS
- Publication number 20150339420
- Publication date Nov 26, 2015
- B.G. Negev Technolgies & Applications Ltd.
- Alexander Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH PHOTONIC ELEMENTS
- Publication number 20150253502
- Publication date Sep 10, 2015
- BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY
- Alexander Fish
- G02 - OPTICS
Information Patent Application
DEVICE AND METHOD FOR DUAL-MODE LOGIC
- Publication number 20140232432
- Publication date Aug 21, 2014
- Alexander Fish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED...
- Publication number 20130170310
- Publication date Jul 4, 2013
- BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY
- Adam TEMAN
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA LOW POWER SRAM CELL CIRCUIT WITH A SUPPLY FEEDBACK LOOP FOR N...
- Publication number 20120281458
- Publication date Nov 8, 2012
- BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY
- Adam TEMAN
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED...
- Publication number 20120281459
- Publication date Nov 8, 2012
- BEN GURION UNIVERSITY OF THE NEGEV RESEARCH AND DEVELOPMENT AUTHORITY
- Adam TEMAN
- G11 - INFORMATION STORAGE

Alexander FISH

Person

Patents Grantslast 30 patents

Secured memory

Information redistribution to reduce side channel leakage

Fin-FET gain cells

Pseudo-asynchronous digital circuit design

Complementary dual-modular redundancy memory cell

Randomized logic against side channel attacks

Pseudo-asynchronous digital circuit design

Data-dependent delay circuits

High-density memory macro

Multi-topology logic gates

Transistor gain cell with feedback

Transistor gain cell with feedback

Dual mode logic circuits

Device and method for dual-mode logic

Ultra low power memory cell with a supply feedback loop configured...

Ultra low power SRAM cell circuit with a supply feedback loop for n...

Patents Applicationslast 30 patents

METHOD FOR MITIGATION OF DROOP TIMING ERRORS INCLUDING A DROOP DETE...

INFORMATION REDISTRIBUTION TO REDUCE SIDE CHANNEL LEAKAGE

FIN-FET GAIN CELLS

SECURED MEMORY

PSEUDO-ASYNCHRONOUS DIGITAL CIRCUIT DESIGN

COMPLEMENTARY DUAL-MODULAR REDUNDANCY MEMORY CELL

PSEUDO- ASYNCHRONOUS DIGITAL CIRCUIT DESIGN

COMPACT BIT GENERATOR

High-density memory macro

RANDOMIZED LOGIC AGAINST SIDE CHANNEL ATTACKS

DATA-DEPENDENT DELAY CIRCUITS

TRANSISTOR GAIN CELL WITH FEEDBACK

MULTI-TOPOLOGY LOGIC GATES

TRANSISTOR GAIN CELL WITH FEEDBACK

DESIGN OF DUAL MODE LOGIC CIRCUITS

INTEGRATED CIRCUIT WITH PHOTONIC ELEMENTS

DEVICE AND METHOD FOR DUAL-MODE LOGIC

ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED...

ULTRA LOW POWER SRAM CELL CIRCUIT WITH A SUPPLY FEEDBACK LOOP FOR N...

ULTRA LOW POWER MEMORY CELL WITH A SUPPLY FEEDBACK LOOP CONFIGURED...