Alexander Korobkov

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit clock tree visualizer
- Patent number 9,275,175
- Issue date Mar 1, 2016
- Oracle International Corporation
- Amit Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit simulation using fundamental and derivative circ...
- Patent number 8,645,883
- Issue date Feb 4, 2014
- Oracle International Corporation
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit clock analysis with macro models
- Patent number 8,464,195
- Issue date Jun 11, 2013
- Oracle International Corporation
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel circuit simulation with partitions
- Patent number 8,341,577
- Issue date Dec 25, 2012
- Oracle International Corporation
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for evaluating a device during circuit simulation
- Patent number 8,190,407
- Issue date May 29, 2012
- Oracle America, Inc.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel power grid analysis
- Patent number 8,024,051
- Issue date Sep 20, 2011
- Oracle America, Inc.
- Alexander Korobkov
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System, method and apparatus for sensitivity based fast power grid...
- Patent number 7,953,581
- Issue date May 31, 2011
- Oracle America, Inc.
- Michael Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast reduction of system models
- Patent number 7,949,970
- Issue date May 24, 2011
- Oracle America, Inc.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance of circuit simulation with multiple combinations of inp...
- Patent number 7,865,348
- Issue date Jan 4, 2011
- Oracle America, Inc.
- Wai Chung W. Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to improve time domain sensitivity analysis performance
- Patent number 7,484,195
- Issue date Jan 27, 2009
- Sun Microsystems, Inc.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graph pruning scheme for sensitivity analysis with partitions
- Patent number 7,421,671
- Issue date Sep 2, 2008
- Sun Microsystems, Inc.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting clock skew for incomplete integ...
- Patent number 7,107,200
- Issue date Sep 12, 2006
- Sun Microsystems, Inc.
- Alexander I. Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing operation on physical design data
- Patent number 6,912,705
- Issue date Jun 28, 2005
- Sun Microsystems, Inc.
- Alexander I. Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit reduction technique for improving clock net analysis perfor...
- Patent number 6,895,524
- Issue date May 17, 2005
- Sun Microsystems, Inc.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for allocating decoupling capacitor cells
- Patent number 6,763,509
- Issue date Jul 13, 2004
- Sun Microsystems, Inc.
- Alexander I. Korobkov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SIMULATING ELECTOSTATIC DISCHARGES
- Publication number 20170032062
- Publication date Feb 2, 2017
- Oracle America, Inc.
- Qing He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT POWER GRID ANALYSIS ON MULTIPLE CPU CORES WITH STATES ELI...
- Publication number 20150339419
- Publication date Nov 26, 2015
- Oracle International Corporation
- Alexander KOROBKOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT CLOCK TREE VISUALIZER
- Publication number 20150227660
- Publication date Aug 13, 2015
- ORACLE INTERNATIONAL CORPORATION
- Amit AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT SIMULATION USING FUNDAMENTAL AND DERIVATIVE CIRC...
- Publication number 20130305201
- Publication date Nov 14, 2013
- ORACLE INTERNATIONAL CORPORATION
- Alexander KOROBKOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL POWER GRID ANALYSIS
- Publication number 20100217577
- Publication date Aug 26, 2010
- SUN MICROSYSTEMS, INC.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING A DEVICE DURING CIRCUIT SIMULATION
- Publication number 20100217569
- Publication date Aug 26, 2010
- SUN MICROSYSTEMS, INC.
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR SENSITIVITY BASED FAST POWER GRID...
- Publication number 20090319250
- Publication date Dec 24, 2009
- Michael Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Graph Pruning Scheme for Sensitivity Analysis with Partitions
- Publication number 20080059922
- Publication date Mar 6, 2008
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for allocating decoupling capacitor cells
- Publication number 20040064800
- Publication date Apr 1, 2004
- Sun Microsystems, Inc., a Delaware Corporation
- Alexander I. Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical reduced-order circuit model for clock net verification
- Publication number 20040059558
- Publication date Mar 25, 2004
- Alexander I Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for performing operation on physical design data
- Publication number 20040003365
- Publication date Jan 1, 2004
- Sun Microsystems, Inc. a Delaware Corporation
- Alexander I. Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prediction method and apparatus for delay and skew analysis
- Publication number 20030144825
- Publication date Jul 31, 2003
- Alexander I Korobkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit reduction technique for improving clock net analysis perfor...
- Publication number 20030065965
- Publication date Apr 3, 2003
- Alexander Korobkov
- G06 - COMPUTING CALCULATING COUNTING

Alexander Korobkov

Person

Patents Grantslast 30 patents

Integrated circuit clock tree visualizer

Integrated circuit simulation using fundamental and derivative circ...

Integrated circuit clock analysis with macro models

Parallel circuit simulation with partitions

Method and system for evaluating a device during circuit simulation

Parallel power grid analysis

System, method and apparatus for sensitivity based fast power grid...

Fast reduction of system models

Performance of circuit simulation with multiple combinations of inp...

Method to improve time domain sensitivity analysis performance

Graph pruning scheme for sensitivity analysis with partitions

Method and apparatus for predicting clock skew for incomplete integ...

Method and apparatus for performing operation on physical design data

Circuit reduction technique for improving clock net analysis perfor...

Method and apparatus for allocating decoupling capacitor cells

Patents Applicationslast 30 patents

SIMULATING ELECTOSTATIC DISCHARGES

EFFICIENT POWER GRID ANALYSIS ON MULTIPLE CPU CORES WITH STATES ELI...

INTEGRATED CIRCUIT CLOCK TREE VISUALIZER

INTEGRATED CIRCUIT SIMULATION USING FUNDAMENTAL AND DERIVATIVE CIRC...

PARALLEL POWER GRID ANALYSIS

METHOD AND SYSTEM FOR EVALUATING A DEVICE DURING CIRCUIT SIMULATION

SYSTEM, METHOD AND APPARATUS FOR SENSITIVITY BASED FAST POWER GRID...

Graph Pruning Scheme for Sensitivity Analysis with Partitions

Method and apparatus for allocating decoupling capacitor cells

Hierarchical reduced-order circuit model for clock net verification

Method and apparatus for performing operation on physical design data

Prediction method and apparatus for delay and skew analysis

Circuit reduction technique for improving clock net analysis perfor...