ALEXANDER V. BUTUZOV

Person

Moscow, RU

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction and logic for identifying instructions for retirement i...
- Patent number 10,133,582
- Issue date Nov 20, 2018
- Intel Corporation
- Nikolay Kosarev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reconstructing real program order of instr...
- Patent number 9,811,340
- Issue date Nov 7, 2017
- Intel Corporation
- Nikolay Kosarev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing area and complexity of instructio...
- Patent number 9,645,819
- Issue date May 9, 2017
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Select logic for the instruction scheduler of a multi strand out-of...
- Patent number 9,632,790
- Issue date Apr 25, 2017
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling instructions in a multi-strand...
- Patent number 9,529,596
- Issue date Dec 27, 2016
- Intel Corporation
- Boris A. Babayan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Scheduling of Instructions in a Multi-Stra...
- Publication number 20170235578
- Publication date Aug 17, 2017
- Intel Corporation
- Boris A. Babayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING PROCESSOR INSTRUCTION WINDOW VIA SEPERATING INSTRUCTIONS...
- Publication number 20170161075
- Publication date Jun 8, 2017
- Intel Corporation
- ALEXANDR TITOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIP...
- Publication number 20160364237
- Publication date Dec 15, 2016
- Intel Corporation
- Nikolay Kosarev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR IDENTIFYING INSTRUCTIONS FOR RETIREMENT I...
- Publication number 20160314000
- Publication date Oct 27, 2016
- Intel Corporation
- Nikolay Kosarev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECT LOGIC FOR THE INSTRUCTION SCHEDULER OF A MULTI STRAND OUT-OF...
- Publication number 20150301831
- Publication date Oct 22, 2015
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR
- Publication number 20140208074
- Publication date Jul 24, 2014
- Boris A. Babayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTIO...
- Publication number 20130339679
- Publication date Dec 19, 2013
- Intel Corporation
- Jayesh IYER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR RECONSTRUCTING REAL PROGRAM ORDER OF INSTR...
- Publication number 20130339711
- Publication date Dec 19, 2013
- Intel Corporation
- Nikolay KOSAREV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SCHEDULING OF INSTRUCTIONS IN A MULTI-STRA...
- Publication number 20130007415
- Publication date Jan 3, 2013
- Boris A. Babayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING
- Publication number 20100274972
- Publication date Oct 28, 2010
- Boris Babayan
- G06 - COMPUTING CALCULATING COUNTING

ALEXANDER V. BUTUZOV

Person

Patents Grantslast 30 patents

Instruction and logic for identifying instructions for retirement i...

Method and apparatus for reconstructing real program order of instr...

Method and apparatus for reducing area and complexity of instructio...

Select logic for the instruction scheduler of a multi strand out-of...

Method and apparatus for scheduling instructions in a multi-strand...

Patents Applicationslast 30 patents

Method and Apparatus for Scheduling of Instructions in a Multi-Stra...

INCREASING PROCESSOR INSTRUCTION WINDOW VIA SEPERATING INSTRUCTIONS...

PROCESSOR LOGIC AND METHOD FOR DISPATCHING INSTRUCTIONS FROM MULTIP...

INSTRUCTION AND LOGIC FOR IDENTIFYING INSTRUCTIONS FOR RETIREMENT I...

SELECT LOGIC FOR THE INSTRUCTION SCHEDULER OF A MULTI STRAND OUT-OF...

INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR

METHOD AND APPARATUS FOR REDUCING AREA AND COMPLEXITY OF INSTRUCTIO...

METHOD AND APPARATUS FOR RECONSTRUCTING REAL PROGRAM ORDER OF INSTR...

METHOD AND APPARATUS FOR SCHEDULING OF INSTRUCTIONS IN A MULTI-STRA...

SYSTEMS, METHODS, AND APPARATUSES FOR PARALLEL COMPUTING