Alexei Galatenko

Person

Moscow, RU

People

Patents Grantslast 30 patents

Information Patent Grant
Low depth combinational finite field multiplier
- Patent number 9,417,847
- Issue date Aug 16, 2016
- Intel Corporation
- Sergey B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified architecture for crypto functional units
- Patent number 8,831,221
- Issue date Sep 9, 2014
- LSI Corporation
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cryptographic processing using a processor
- Patent number 8,452,006
- Issue date May 28, 2013
- LSI Corporation
- Dmitriy Vladimirovich Alekseev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hash processing using a processor
- Patent number 8,447,988
- Issue date May 21, 2013
- LSI Corporation
- Dmitriy Vladimirovich Alekseev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture and implementation method of programmable arithmetic c...
- Patent number 8,302,083
- Issue date Oct 30, 2012
- LSI Corporation
- Anatoli A. Bolotov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of arithmetical secure hash techniques
- Patent number 8,160,242
- Issue date Apr 17, 2012
- LSI Corporation
- Mikhail Grinchuk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Ramptime propagation on designs with cycles
- Patent number 7,568,175
- Issue date Jul 28, 2009
- LSI Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of selecting cells in logic restructuring
- Patent number 7,496,870
- Issue date Feb 24, 2009
- LSI Corporation
- Iliya V. Lyalin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling congestion during integrated c...
- Patent number 7,401,313
- Issue date Jul 15, 2008
- LSI Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing logical transformations for glo...
- Patent number 7,398,486
- Issue date Jul 8, 2008
- LSI Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple buffer insertion in global routing
- Patent number 7,257,791
- Issue date Aug 14, 2007
- LSI Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ramptime propagation on designs with cycles
- Patent number 7,246,336
- Issue date Jul 17, 2007
- LSI Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of selecting cells in logic restructuring
- Patent number 7,146,591
- Issue date Dec 5, 2006
- LSI Logic Corporation
- Iliya V. Lyalin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process and apparatus to assign coordinates to nodes of logical tre...
- Patent number 7,111,267
- Issue date Sep 19, 2006
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process and apparatus for placement of megacells in ICs design
- Patent number 7,103,865
- Issue date Sep 5, 2006
- LSI Logic Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for finding optimal unification substitution f...
- Patent number 7,003,739
- Issue date Feb 21, 2006
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURE AND IMPLEMENTATION METHOD OF PROGRAMMABLE ARITHMETIC C...
- Publication number 20130024668
- Publication date Jan 24, 2013
- LSI Corporation
- Anatoli Bolotov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER
- Publication number 20120226731
- Publication date Sep 6, 2012
- Sergey B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HASH PROCESSING USING A PROCESSOR
- Publication number 20120166773
- Publication date Jun 28, 2012
- LSI Corporation
- Dmitriy Vladimirovich Alekseev
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS
- Publication number 20120076298
- Publication date Mar 29, 2012
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CRYPTOGRAPHIC PROCESSING USING A PROCESSOR
- Publication number 20110231673
- Publication date Sep 22, 2011
- LSI Corporation
- Dmitriy Vladimirovich Alekseev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture and implementation method of programmable arithmetic c...
- Publication number 20100191935
- Publication date Jul 29, 2010
- Anatoli A. Bolotov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES
- Publication number 20100086127
- Publication date Apr 8, 2010
- Mikhail Grinchuk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES
- Publication number 20070234255
- Publication date Oct 4, 2007
- LSI Logic Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling congestion during integrated c...
- Publication number 20070094631
- Publication date Apr 26, 2007
- LSI Logic Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING
- Publication number 20070050744
- Publication date Mar 1, 2007
- LSI Logic Corporation
- Iliya V. Lyalin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ramptime propagation on designs with cycles
- Publication number 20060123369
- Publication date Jun 8, 2006
- LSI Logic Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of selecting cells in logic restructuring
- Publication number 20060112361
- Publication date May 25, 2006
- LSI Logic Corporation
- Iliya V. Lyalin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple buffer insertion in global routing
- Publication number 20060112363
- Publication date May 25, 2006
- LSI Logic Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process and apparatus to assign coordinates to nodes of logical tre...
- Publication number 20060048087
- Publication date Mar 2, 2006
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for performing logical transformations for glo...
- Publication number 20050210422
- Publication date Sep 22, 2005
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for finding optimal unification substitution f...
- Publication number 20050114804
- Publication date May 26, 2005
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process and apparatus for placement of megacells in ICs design
- Publication number 20050114813
- Publication date May 26, 2005
- LSI Logic Corporation
- Alexei V. Galatenko
- G06 - COMPUTING CALCULATING COUNTING

Alexei Galatenko

Person

Patents Grantslast 30 patents

Low depth combinational finite field multiplier

Unified architecture for crypto functional units

Cryptographic processing using a processor

Hash processing using a processor

Architecture and implementation method of programmable arithmetic c...

Efficient implementation of arithmetical secure hash techniques

Ramptime propagation on designs with cycles

Method of selecting cells in logic restructuring

Method and apparatus for controlling congestion during integrated c...

Method and apparatus for performing logical transformations for glo...

Multiple buffer insertion in global routing

Ramptime propagation on designs with cycles

Method of selecting cells in logic restructuring

Process and apparatus to assign coordinates to nodes of logical tre...

Process and apparatus for placement of megacells in ICs design

Method and apparatus for finding optimal unification substitution f...

Patents Applicationslast 30 patents

ARCHITECTURE AND IMPLEMENTATION METHOD OF PROGRAMMABLE ARITHMETIC C...

LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER

HASH PROCESSING USING A PROCESSOR

UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS

CRYPTOGRAPHIC PROCESSING USING A PROCESSOR

Architecture and implementation method of programmable arithmetic c...

EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES

RAMPTIME PROPAGATION ON DESIGNS WITH CYCLES

Method and apparatus for controlling congestion during integrated c...

METHOD OF SELECTING CELLS IN LOGIC RESTRUCTURING

Ramptime propagation on designs with cycles

Method of selecting cells in logic restructuring

Multiple buffer insertion in global routing

Process and apparatus to assign coordinates to nodes of logical tre...

Method and apparatus for performing logical transformations for glo...

Method and apparatus for finding optimal unification substitution f...

Process and apparatus for placement of megacells in ICs design