Alexey P. Suprun

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Accelerator for sparse-dense matrix multiplication
- Patent number 11,829,440
- Issue date Nov 28, 2023
- Intel Corporation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for memory interface circuit arbi...
- Patent number 11,037,050
- Issue date Jun 15, 2021
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerator for sparse-dense matrix multiplication
- Patent number 10,984,074
- Issue date Apr 20, 2021
- Intel Corporation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerator for sparse-dense matrix multiplication
- Patent number 10,867,009
- Issue date Dec 15, 2020
- Intel Corporation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerator for sparse-dense matrix multiplication
- Patent number 10,572,568
- Issue date Feb 25, 2020
- Intel Corporation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resolving memory accesses crossing cache line boundaries
- Patent number 10,318,427
- Issue date Jun 11, 2019
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 10,175,986
- Issue date Jan 8, 2019
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing an efficient scatter
- Patent number 9,891,914
- Issue date Feb 13, 2018
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable event handling in multi-threaded processor cores
- Patent number 9,886,396
- Issue date Feb 6, 2018
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stateless capture of data linear addresses during precise event bas...
- Patent number 9,652,237
- Issue date May 16, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
- Publication number 20240070226
- Publication date Feb 29, 2024
- Intel Corporation
- Srinivasan NARAYANAMOORTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
- Publication number 20210342417
- Publication date Nov 4, 2021
- Intel Corporation
- Srinivasan NARAYANAMOORTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY INTERFACE CIRCUIT ARBI...
- Publication number 20200410323
- Publication date Dec 31, 2020
- Intel Corporation
- Krishna N. Vinod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
- Publication number 20200334323
- Publication date Oct 22, 2020
- Intel Corporation
- Srinivasan NARAYANAMOORTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
- Publication number 20200265107
- Publication date Aug 20, 2020
- Intel Corporation
- Srinivasan NARAYANAMOORTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
- Publication number 20190042542
- Publication date Feb 7, 2019
- Intel Corporation
- Srinivasan NARAYANAMOORTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20170242698
- Publication date Aug 24, 2017
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER
- Publication number 20160299762
- Publication date Oct 13, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES
- Publication number 20160179677
- Publication date Jun 23, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
- Publication number 20160179533
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...
- Publication number 20160179541
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING

Alexey P. Suprun

Person

Patents Grantslast 30 patents

Accelerator for sparse-dense matrix multiplication

Apparatuses, methods, and systems for memory interface circuit arbi...

Accelerator for sparse-dense matrix multiplication

Accelerator for sparse-dense matrix multiplication

Accelerator for sparse-dense matrix multiplication

Resolving memory accesses crossing cache line boundaries

Stateless capture of data linear addresses during precise event bas...

Method and apparatus for performing an efficient scatter

Scalable event handling in multi-threaded processor cores

Stateless capture of data linear addresses during precise event bas...

Patents Applicationslast 30 patents

ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY INTERFACE CIRCUIT ARBI...

ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...

METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER

RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BAS...