Alfred Larry Crouch

Person

Travis, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, system, and apparatus for security assurance, protection, m...
- Patent number 12,026,250
- Issue date Jul 2, 2024
- Amida Technology Solutions, Inc.
- Alfred L Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for security assurance, protection, m...
- Patent number 11,736,501
- Issue date Aug 22, 2023
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using embedded time-varying code generator to provide secure access...
- Patent number 11,693,052
- Issue date Jul 4, 2023
- Silicon Aid Solutions, Inc.
- James M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system and apparatus for security assurance, protection, mo...
- Patent number 11,681,795
- Issue date Jun 20, 2023
- Amida Technology Solutions, Inc.
- Alfred L. Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using embedded time-varying code generator to provide secure access...
- Patent number 11,333,706
- Issue date May 17, 2022
- Silicon Aid Solutions, Inc.
- James M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for verification of operation using G...
- Patent number 11,277,419
- Issue date Mar 15, 2022
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for selection of location for placement of trojan...
- Patent number 11,157,619
- Issue date Oct 26, 2021
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for selection of location for placement of trojan...
- Patent number 10,909,284
- Issue date Feb 2, 2021
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using embedded time-varying code generator to provide secure access...
- Patent number 10,690,718
- Issue date Jun 23, 2020
- SiliconAid Solutions, Inc.
- James M. Johnson
- G01 - MEASURING TESTING
Information Patent Grant
Protecting hidden content in integrated circuits
- Patent number 9,811,690
- Issue date Nov 7, 2017
- Southern Methodist University
- Jennifer L. Dworak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protection of proprietary embedded instruments
- Patent number 9,305,186
- Issue date Apr 5, 2016
- Asset Intertech, Inc.
- Alfred L. Crouch
- G01 - MEASURING TESTING
Information Patent Grant
Protection of proprietary embedded instruments
- Patent number 8,881,301
- Issue date Nov 4, 2014
- Asset Intertech, Inc.
- Alfred L. Crouch
- G01 - MEASURING TESTING
Information Patent Grant
Process for improving design-limited yield by localizing potential...
- Patent number 8,615,691
- Issue date Dec 24, 2013
- Advantest (Singapore) Pte Ltd
- Richard C Dokken
- G01 - MEASURING TESTING
Information Patent Grant
Method for operating a secure semiconductor IP server to support fa...
- Patent number 8,060,851
- Issue date Nov 15, 2011
- Verigy (Singapore) Pte. Ltd.
- Richard C. Dokken
- G01 - MEASURING TESTING
Information Patent Grant
Methods for analyzing scan chains, and for determining numbers or l...
- Patent number 8,010,856
- Issue date Aug 30, 2011
- Verigy (Singapore) Pte. Ltd.
- Stephen A. Cannon
- G01 - MEASURING TESTING
Information Patent Grant
Locating hold time violations in scan chains by generating patterns...
- Patent number 7,853,846
- Issue date Dec 14, 2010
- Verigy (Singapore) Pte. Ltd.
- Stephen A. Cannon
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for network-on-chip and other integrated circuit...
- Patent number 7,348,796
- Issue date Mar 25, 2008
- Dafca, Inc.
- Alfred L. Crouch
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test access mechanism for supporting a configurable built-in self-t...
- Patent number 6,701,476
- Issue date Mar 2, 2004
- Motorola, Inc.
- Bahram Pouya
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing an integrated circuit
- Patent number 6,598,192
- Issue date Jul 22, 2003
- Motorola, Inc.
- Teresa L. McLaurin
- G01 - MEASURING TESTING
Information Patent Grant
Multiple BIST controllers for testing multiple embedded memory arrays
- Patent number 5,995,731
- Issue date Nov 30, 1999
- Motorola, Inc.
- Alfred Larry Crouch
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing operative testing on an integra...
- Patent number 5,929,650
- Issue date Jul 27, 1999
- Motorola, Inc.
- Bernard J. Pappert
- G01 - MEASURING TESTING
Information Patent Grant
Wrapper cell architecture for path delay testing of embedded core m...
- Patent number 5,889,788
- Issue date Mar 30, 1999
- Motorola, Inc.
- Matthew D. Pressly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan based testing of an integrated circuit for compliance with tim...
- Patent number 5,812,561
- Issue date Sep 22, 1998
- Motorola, Inc.
- Grady L. Giles
- G01 - MEASURING TESTING
Information Patent Grant
Scannable storage cell and method of operation
- Patent number 5,719,878
- Issue date Feb 17, 1998
- Motorola Inc.
- Ruey J. Yu
- G01 - MEASURING TESTING
Information Patent Grant
Method for creating a high speed scan-interconnected set of flip-fl...
- Patent number 5,717,700
- Issue date Feb 10, 1998
- Motorola, Inc.
- Alfred L. Crouch
- G01 - MEASURING TESTING
Information Patent Grant
Data Processor having a built-in internal self test controller for...
- Patent number 5,617,531
- Issue date Apr 1, 1997
- Motorola, Inc.
- Alfred L. Crouch
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial scan chain architecture for a data processing system and met...
- Patent number 5,592,493
- Issue date Jan 7, 1997
- Motorola Inc.
- Alfred L. Crouch
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing pin isolation for an integrated ci...
- Patent number 5,561,614
- Issue date Oct 1, 1996
- Motorola Inc.
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing a clock stopping/starting function...
- Patent number 5,553,236
- Issue date Sep 3, 1996
- Motorola, Inc.
- Juan G. Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self re-seeding linear feedback shift register (LFSR) data processi...
- Patent number 5,383,143
- Issue date Jan 17, 1995
- Motorola, Inc.
- Alfred L. Crouch
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...
- Publication number 20240143743
- Publication date May 2, 2024
- Amida Technology Solutions, Inc.
- Alfred L. Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Embedded Time-Varying Code Generator to Provide Secure Access...
- Publication number 20220244311
- Publication date Aug 4, 2022
- SiliconAid Solutions, Inc.
- James M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR INSERTION OF CYBERSECURITY AND HARDWARE ASSUR...
- Publication number 20220164437
- Publication date May 26, 2022
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...
- Publication number 20220030013
- Publication date Jan 27, 2022
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR VERIFICATION OF OPERATION USING G...
- Publication number 20220026580
- Publication date Jan 27, 2022
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Selection of Location for Placement of Trojan...
- Publication number 20210200868
- Publication date Jul 1, 2021
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, MO...
- Publication number 20200104485
- Publication date Apr 2, 2020
- Amida Technology Solutions, Inc.
- Alfred L. Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...
- Publication number 20200104497
- Publication date Apr 2, 2020
- Amida Technology Solutions, Inc.
- Alfred Larry Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Embedded Time-Varying Code Generator to Provide Secure Access...
- Publication number 20190086472
- Publication date Mar 21, 2019
- SiliconAid Solutions, Inc.
- James M. Johnson
- G01 - MEASURING TESTING
Information Patent Application
Using Embedded Time-Varying Code Generator to Provide Secure Access...
- Publication number 20170131355
- Publication date May 11, 2017
- SiliconAid Solutions, Inc.
- James M. Johnson
- G01 - MEASURING TESTING
Information Patent Application
Protecting Hidden Content In Integrated Circuits
- Publication number 20150349968
- Publication date Dec 3, 2015
- Southern Methodist University
- Jennifer L. Dworak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTECTION OF PROPRIETARY EMBEDDED INSTRUMENTS
- Publication number 20150026822
- Publication date Jan 22, 2015
- ASSET InterTech, Inc.
- Alfred L. Crouch
- G01 - MEASURING TESTING
Information Patent Application
PROTECTION OF PROPRIETARY EMBEDDED INSTRUMENTS
- Publication number 20110083195
- Publication date Apr 7, 2011
- Alfred L. Crouch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FA...
- Publication number 20100031092
- Publication date Feb 4, 2010
- Inovys Corporation
- RICHARD C. DOKKEN
- G01 - MEASURING TESTING
Information Patent Application
METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR L...
- Publication number 20090113263
- Publication date Apr 30, 2009
- Stephen A. Cannon
- G01 - MEASURING TESTING
Information Patent Application
LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS...
- Publication number 20090113265
- Publication date Apr 30, 2009
- Inovys Corporation
- Stephen A. Cannon
- G01 - MEASURING TESTING
Information Patent Application
PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL...
- Publication number 20080091981
- Publication date Apr 17, 2008
- Inovys Corporation
- RICHARD C. DOKKEN
- G01 - MEASURING TESTING
Information Patent Application
Method and system for network-on-chip and other integrated circuit...
- Publication number 20070113123
- Publication date May 17, 2007
- Alfred L. Crouch
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Test access mechanism for supporting a configurable built-in self-t...
- Publication number 20020184582
- Publication date Dec 5, 2002
- Bahram Pouya
- G01 - MEASURING TESTING

Alfred Larry Crouch

Person

Patents Grantslast 30 patents

Method, system, and apparatus for security assurance, protection, m...

Method, system, and apparatus for security assurance, protection, m...

Using embedded time-varying code generator to provide secure access...

Method, system and apparatus for security assurance, protection, mo...

Using embedded time-varying code generator to provide secure access...

Method, system, and apparatus for verification of operation using G...

Method and system for selection of location for placement of trojan...

Method and system for selection of location for placement of trojan...

Using embedded time-varying code generator to provide secure access...

Protecting hidden content in integrated circuits

Protection of proprietary embedded instruments

Protection of proprietary embedded instruments

Process for improving design-limited yield by localizing potential...

Method for operating a secure semiconductor IP server to support fa...

Methods for analyzing scan chains, and for determining numbers or l...

Locating hold time violations in scan chains by generating patterns...

Method and system for network-on-chip and other integrated circuit...

Test access mechanism for supporting a configurable built-in self-t...

Method and apparatus for testing an integrated circuit

Multiple BIST controllers for testing multiple embedded memory arrays

Method and apparatus for performing operative testing on an integra...

Wrapper cell architecture for path delay testing of embedded core m...

Scan based testing of an integrated circuit for compliance with tim...

Scannable storage cell and method of operation

Method for creating a high speed scan-interconnected set of flip-fl...

Data Processor having a built-in internal self test controller for...

Serial scan chain architecture for a data processing system and met...

Method and apparatus for testing pin isolation for an integrated ci...

Method and apparatus for testing a clock stopping/starting function...

Self re-seeding linear feedback shift register (LFSR) data processi...

Patents Applicationslast 30 patents

METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...

Using Embedded Time-Varying Code Generator to Provide Secure Access...

METHOD AND SYSTEM FOR INSERTION OF CYBERSECURITY AND HARDWARE ASSUR...

METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...

METHOD, SYSTEM, AND APPARATUS FOR VERIFICATION OF OPERATION USING G...

Method and System for Selection of Location for Placement of Trojan...

METHOD, SYSTEM AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, MO...

METHOD, SYSTEM, AND APPARATUS FOR SECURITY ASSURANCE, PROTECTION, M...

Using Embedded Time-Varying Code Generator to Provide Secure Access...

Using Embedded Time-Varying Code Generator to Provide Secure Access...

Protecting Hidden Content In Integrated Circuits

PROTECTION OF PROPRIETARY EMBEDDED INSTRUMENTS

PROTECTION OF PROPRIETARY EMBEDDED INSTRUMENTS

METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FA...

METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR L...

LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS...

PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL...

Method and system for network-on-chip and other integrated circuit...

Test access mechanism for supporting a configurable built-in self-t...