Ali El-Zein

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Signal pre-routing in an integrated circuit design
- Patent number 12,050,852
- Issue date Jul 30, 2024
- International Business Machines Corporation
- Wolfgang Roesner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock mapping in an integrated circuit design
- Patent number 11,663,381
- Issue date May 30, 2023
- International Business Machines Corporation
- Stephen Gerard Shuma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pin cloning and subway creation on automatically generated design p...
- Patent number 10,599,804
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Equivalency verification for hierarchical references
- Patent number 10,565,338
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-invasive insertion of logic functions into a register-transfer...
- Patent number 9,495,496
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Stephen J. Barnfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizing VHDL multiple wait FSMS into RT level FSMS by preproce...
- Patent number 8,713,494
- Issue date Apr 29, 2014
- International Business Machines Corporation
- Gabor Bobok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit verification using computational algebraic geometry
- Patent number 8,640,065
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Gradus (Geert) Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...
- Patent number 8,495,533
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abstraction level-preserving conversion of flip-flop-inferred hardw...
- Patent number 8,443,314
- Issue date May 14, 2013
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Co-optimization of embedded systems utilizing symbolic execution
- Patent number 8,234,604
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Ali S El-Zein
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Compiler option consistency checking during incremental hardware de...
- Patent number 8,230,406
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Richard L. H. Carbone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for modeling variables in subprograms of hardware descri...
- Patent number 8,140,313
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential encoding for relational analysis (SERA) of a software model
- Patent number 8,141,048
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Jason R. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unrolling hardware design generate statements in a source window de...
- Patent number 7,823,097
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and program product for pre-compile processing of h...
- Patent number 7,506,287
- Issue date Mar 17, 2009
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reconfiguration of random biases in a synthesized design...
- Patent number 7,284,210
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Jason Raymond Baumgartner
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EARLY POWER ESTIMATION ON A DERIVED PHYSICAL HIERARCHY IN CHIP DESIGN
- Publication number 20240152676
- Publication date May 9, 2024
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL PRE-ROUTING IN AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230075565
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Wolfgang Roesner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFINEMENT OF AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230072735
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MAPPING IN AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230075770
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Stephen Gerard Shuma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230070516
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN
- Publication number 20230074528
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EQUIVALENCY VERIFICATION FOR HIERARCHICAL REFERENCES
- Publication number 20190179974
- Publication date Jun 13, 2019
- International Business Machines Corporation
- Ali S. El-Zein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-INVASIVE INSERTION OF LOGIC FUNCTIONS INTO A REGISTER-TRANSFER...
- Publication number 20160180000
- Publication date Jun 23, 2016
- International Business Machines Corporation
- STEPHEN J. BARNFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCE...
- Publication number 20130275930
- Publication date Oct 17, 2013
- Gabor Bobok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
- Publication number 20130198705
- Publication date Aug 1, 2013
- International Business Machines Corporation
- Gradus (Geert) Janssen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CO-OPTIMIZATION OF EMBEDDED SYSTEMS UTILIZING SYMBOLIC EXECUTION
- Publication number 20100058256
- Publication date Mar 4, 2010
- International Business Machines Corporation
- ALI S. EL-ZEIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, System and Program Product Supporting Sequential Encoding f...
- Publication number 20080209389
- Publication date Aug 28, 2008
- Jason R. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...
- Publication number 20080127126
- Publication date May 29, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compiler Option Consistency Checking During Incremental Hardware De...
- Publication number 20080127130
- Publication date May 29, 2008
- International Business Machines Corporation
- Richard L.H. Carbone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, system, and program product for pre-compile processing of H...
- Publication number 20080072187
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unrolling Hardware Design Generate Statements in a Source Window De...
- Publication number 20080072206
- Publication date Mar 20, 2008
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for reconfiguration of random biases in a synthesized design...
- Publication number 20060190867
- Publication date Aug 24, 2006
- Jason Raymond Baumgartner
- G06 - COMPUTING CALCULATING COUNTING

Ali El-Zein

Person

Patents Grantslast 30 patents

Signal pre-routing in an integrated circuit design

Clock mapping in an integrated circuit design

Pin cloning and subway creation on automatically generated design p...

Equivalency verification for hierarchical references

Non-invasive insertion of logic functions into a register-transfer...

Synthesizing VHDL multiple wait FSMS into RT level FSMS by preproce...

Circuit verification using computational algebraic geometry

Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...

Abstraction level-preserving conversion of flip-flop-inferred hardw...

Co-optimization of embedded systems utilizing symbolic execution

Compiler option consistency checking during incremental hardware de...

Techniques for modeling variables in subprograms of hardware descri...

Sequential encoding for relational analysis (SERA) of a software model

Unrolling hardware design generate statements in a source window de...

Method, system, and program product for pre-compile processing of h...

Method for reconfiguration of random biases in a synthesized design...

Patents Applicationslast 30 patents

EARLY POWER ESTIMATION ON A DERIVED PHYSICAL HIERARCHY IN CHIP DESIGN

SIGNAL PRE-ROUTING IN AN INTEGRATED CIRCUIT DESIGN

REFINEMENT OF AN INTEGRATED CIRCUIT DESIGN

CLOCK MAPPING IN AN INTEGRATED CIRCUIT DESIGN

LOGICAL CLOCK CONNECTION IN AN INTEGRATED CIRCUIT DESIGN

ITERATIVE DESIGN OF AN INTEGRATED CIRCUIT DESIGN

EQUIVALENCY VERIFICATION FOR HIERARCHICAL REFERENCES

NON-INVASIVE INSERTION OF LOGIC FUNCTIONS INTO A REGISTER-TRANSFER...

SYNTHESIZING VHDL MULTIPLE WAIT FSMS INTO RT LEVEL FSMS BY PREPROCE...

CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY

CO-OPTIMIZATION OF EMBEDDED SYSTEMS UTILIZING SYMBOLIC EXECUTION

Method, System and Program Product Supporting Sequential Encoding f...

Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs...

Compiler Option Consistency Checking During Incremental Hardware De...

Method, system, and program product for pre-compile processing of H...

Unrolling Hardware Design Generate Statements in a Source Window De...

Method for reconfiguration of random biases in a synthesized design...