Ali Ghalam

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data bus duty cycle distortion compensation
- Patent number 11,768,782
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus duty cycle distortion compensation
- Patent number 11,442,877
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal clock distortion calibration using DC component offset of...
- Patent number 11,336,265
- Issue date May 17, 2022
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal clock distortion calibration using DC component offset of...
- Patent number 10,972,078
- Issue date Apr 6, 2021
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internal clock distortion calibration using dc component offset of...
- Patent number 10,727,816
- Issue date Jul 28, 2020
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for serializing data output
- Patent number 10,658,041
- Issue date May 19, 2020
- Micron Technology, Inc.
- Luigi Pilolli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Skew reduction of a wave pipeline in a memory device
- Patent number 10,410,698
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- Kaveh Shakeri
- G11 - INFORMATION STORAGE
Information Patent Grant
Wave pipeline
- Patent number 10,360,956
- Issue date Jul 23, 2019
- Micron Technology, Inc.
- Kaveh Shakeri
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal clock distortion calibration using DC component offset of...
- Patent number 10,270,429
- Issue date Apr 23, 2019
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a memory die architecture including an...
- Patent number 9,710,182
- Issue date Jul 18, 2017
- Micron Technology, Inc.
- Dean K. Nobunaga
- G11 - INFORMATION STORAGE
Information Patent Grant
Auto-suspend and auto-resume operations for a multi-die NAND memory...
- Patent number 9,443,600
- Issue date Sep 13, 2016
- Intel Corporation
- Ali Ghalam
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices and systems including enabling circuits
- Patent number 9,401,188
- Issue date Jul 26, 2016
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for a memory die architecture including an...
- Patent number 9,190,133
- Issue date Nov 17, 2015
- Micron Technology, Inc.
- Dean K. Nobunaga
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices and systems including enabling circuits
- Patent number 8,675,420
- Issue date Mar 18, 2014
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for addressing memory arrays
- Patent number 8,462,536
- Issue date Jun 11, 2013
- Intel Corporation
- Dean Nobunaga
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
WRITE TRAINING IN MEMORY DEVICES
- Publication number 20240012573
- Publication date Jan 11, 2024
- Lodestar Licensing Group, LLC
- Luigi Pilolli
- G11 - INFORMATION STORAGE
Information Patent Application
DATA BURST QUEUE MANAGEMENT
- Publication number 20230367723
- Publication date Nov 16, 2023
- Micron Technology, Inc.
- Eric N. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUS DUTY CYCLE DISTORTION COMPENSATION
- Publication number 20220374370
- Publication date Nov 24, 2022
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUS DUTY CYCLE DISTORTION COMPENSATION
- Publication number 20220138120
- Publication date May 5, 2022
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...
- Publication number 20210218388
- Publication date Jul 15, 2021
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING ATTRIBUTES OF MEMORY COMPONENTS
- Publication number 20210064278
- Publication date Mar 4, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...
- Publication number 20200336135
- Publication date Oct 22, 2020
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR SERIALIZING DATA OUTPUT
- Publication number 20200176059
- Publication date Jun 4, 2020
- Micron Technology, Inc.
- Luigi Pilolli
- G11 - INFORMATION STORAGE
Information Patent Application
INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...
- Publication number 20190190501
- Publication date Jun 20, 2019
- Micron Technology, Inc.
- Guan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAVE PIPELINE
- Publication number 20190180801
- Publication date Jun 13, 2019
- Micron Technology, Inc.
- Kaveh Shakeri
- G11 - INFORMATION STORAGE
Information Patent Application
WAVE PIPELINE
- Publication number 20190180802
- Publication date Jun 13, 2019
- Micron Technology, Inc.
- Kaveh Shakeri
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN...
- Publication number 20160070504
- Publication date Mar 10, 2016
- Micron Technology, Inc.
- Dean K. Nobunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory...
- Publication number 20140293704
- Publication date Oct 2, 2014
- Ali Ghalam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE
- Publication number 20140258619
- Publication date Sep 11, 2014
- Micron Technology, Inc.
- Dean K. Nobunaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS
- Publication number 20140198586
- Publication date Jul 17, 2014
- Micron Technology, Inc.
- Toru Tanzawa
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ADDRESSING MEMORY ARRAYS
- Publication number 20120230110
- Publication date Sep 13, 2012
- Dean Nobunaga
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Data bus duty cycle distortion compensation

Data bus duty cycle distortion compensation

Internal clock distortion calibration using DC component offset of...

Internal clock distortion calibration using DC component offset of...

Internal clock distortion calibration using dc component offset of...

Apparatus and methods for serializing data output

Skew reduction of a wave pipeline in a memory device

Wave pipeline

Internal clock distortion calibration using DC component offset of...

Apparatuses and methods for a memory die architecture including an...

Auto-suspend and auto-resume operations for a multi-die NAND memory...

Devices and systems including enabling circuits

Apparatuses and methods for a memory die architecture including an...

Devices and systems including enabling circuits

Method and apparatus for addressing memory arrays

Patents Applicationslast 30 patents

WRITE TRAINING IN MEMORY DEVICES

DATA BURST QUEUE MANAGEMENT

DATA BUS DUTY CYCLE DISTORTION COMPENSATION

DATA BUS DUTY CYCLE DISTORTION COMPENSATION

INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...

MANAGING ATTRIBUTES OF MEMORY COMPONENTS

INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...

APPARATUS AND METHODS FOR SERIALIZING DATA OUTPUT

INTERNAL CLOCK DISTORTION CALIBRATION USING DC COMPONENT OFFSET OF...

WAVE PIPELINE

WAVE PIPELINE

APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN...

Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory...

APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE

DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS

METHOD AND APPARATUS FOR ADDRESSING MEMORY ARRAYS