Alireza S. Kaviani

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer-scale large programmable device
- Patent number 11,803,681
- Issue date Oct 31, 2023
- Xilinx, Inc.
- Zachary Blair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet-based and time-multiplexed network-on-chip
- Patent number 11,496,418
- Issue date Nov 8, 2022
- Xilinx, Inc.
- Zachary Blair
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Active-by-active programmable device
- Patent number RE49163
- Issue date Aug 9, 2022
- Xilinx, Inc.
- Alireza S. Kaviani
Information Patent Grant
Die-to-die communications scheme
- Patent number 10,498,567
- Issue date Dec 3, 2019
- Xilinx, Inc.
- Alireza S. Kaviani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System-level interconnect ring for a programmable integrated circuit
- Patent number 10,042,806
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active-by-active programmable device
- Patent number 10,002,100
- Issue date Jun 19, 2018
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folding duplicate instances of modules in a circuit design
- Patent number 9,875,330
- Issue date Jan 23, 2018
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lut cascading circuit
- Patent number 9,602,108
- Issue date Mar 21, 2017
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data-driven pattern matching in synthesis of circuit designs
- Patent number 8,938,700
- Issue date Jan 20, 2015
- Xilinx, Inc.
- Elliott Delaye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuit and method of asynchronously routin...
- Patent number 8,913,601
- Issue date Dec 16, 2014
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of and circuit for generating a spread spectrum clock signal
- Patent number 8,831,064
- Issue date Sep 9, 2014
- Xilinx, Inc.
- Alireza S. Kaviani
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for providing digital frequency synthesis
- Patent number 8,788,553
- Issue date Jul 22, 2014
- Xilinx, Inc.
- Ted Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit and method of asynchronously routin...
- Patent number 8,358,148
- Issue date Jan 22, 2013
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit and method of asynchronously routing data in an...
- Patent number 8,294,490
- Issue date Oct 23, 2012
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for digital frequency synthesis in an integrated circuit
- Patent number 7,479,814
- Issue date Jan 20, 2009
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure for the main oscillator of a counter-controlled delay line
- Patent number 7,477,112
- Issue date Jan 13, 2009
- Xilinx, Inc.
- Tao Pi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of and circuit for deskewing clock signals in an integrated...
- Patent number 7,453,297
- Issue date Nov 18, 2008
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of and circuit for phase shifting a clock signal
- Patent number 7,453,301
- Issue date Nov 18, 2008
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for and method of generating a frequency aligned clock signal
- Patent number 7,236,026
- Issue date Jun 26, 2007
- Xilinx, Inc.
- Maheen A. Samad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid counter with an asynchronous front end
- Patent number 7,190,756
- Issue date Mar 13, 2007
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-edge synchronized data sampler
- Patent number 7,190,196
- Issue date Mar 13, 2007
- Xilinx, Inc.
- Alireza S. Kaviani
- G11 - INFORMATION STORAGE
Information Patent Grant
Counter-controlled delay line
- Patent number 7,071,751
- Issue date Jul 4, 2006
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Literal sharing method for fast sum-of-products logic
- Patent number 6,978,427
- Issue date Dec 20, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard phase alignment of clock signals with an oscillator controller
- Patent number 6,943,597
- Issue date Sep 13, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure for reducing leakage current in submicron IC devices
- Patent number 6,914,449
- Issue date Jul 5, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for glitchless clock control
- Patent number 6,873,183
- Issue date Mar 29, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing jitter and power dissipation in a...
- Patent number 6,847,246
- Issue date Jan 25, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DCVSL pulse width controller and system
- Patent number 6,838,919
- Issue date Jan 4, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hard phase alignment of clock signals using asynchronous level-mode...
- Patent number 6,838,918
- Issue date Jan 4, 2005
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA with improved structure for implementing large multiplexers
- Patent number 6,806,732
- Issue date Oct 19, 2004
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM-LEVEL INTERCONNECT RING FOR A PROGRAMMABLE INTEGRATED CIRCUIT
- Publication number 20170220508
- Publication date Aug 3, 2017
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE
- Publication number 20170220509
- Publication date Aug 3, 2017
- Xilinx, Inc.
- Alireza S. Kaviani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN
- Publication number 20170161419
- Publication date Jun 8, 2017
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structure for reducing leakage current in submicron IC devices
- Publication number 20020141234
- Publication date Oct 3, 2002
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic block for PLD with logic gate for combining outp...
- Publication number 20020079921
- Publication date Jun 27, 2002
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY

Alireza S. Kaviani

Person

Patents Grantslast 30 patents

Wafer-scale large programmable device

Packet-based and time-multiplexed network-on-chip

Active-by-active programmable device

Die-to-die communications scheme

System-level interconnect ring for a programmable integrated circuit

Active-by-active programmable device

Folding duplicate instances of modules in a circuit design

Lut cascading circuit

Data-driven pattern matching in synthesis of circuit designs

Programmable integrated circuit and method of asynchronously routin...

Method of and circuit for generating a spread spectrum clock signal

Method and circuit for providing digital frequency synthesis

Programmable integrated circuit and method of asynchronously routin...

Integrated circuit and method of asynchronously routing data in an...

Circuit for digital frequency synthesis in an integrated circuit

Structure for the main oscillator of a counter-controlled delay line

Method of and circuit for deskewing clock signals in an integrated...

Method of and circuit for phase shifting a clock signal

Circuit for and method of generating a frequency aligned clock signal

Hybrid counter with an asynchronous front end

Dual-edge synchronized data sampler

Counter-controlled delay line

Literal sharing method for fast sum-of-products logic

Hard phase alignment of clock signals with an oscillator controller

Structure for reducing leakage current in submicron IC devices

Method and circuit for glitchless clock control

Method and apparatus for reducing jitter and power dissipation in a...

DCVSL pulse width controller and system

Hard phase alignment of clock signals using asynchronous level-mode...

FPGA with improved structure for implementing large multiplexers

Patents Applicationslast 30 patents

SYSTEM-LEVEL INTERCONNECT RING FOR A PROGRAMMABLE INTEGRATED CIRCUIT

ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE

FOLDING DUPLICATE INSTANCES OF MODULES IN A CIRCUIT DESIGN

Structure for reducing leakage current in submicron IC devices

Configurable logic block for PLD with logic gate for combining outp...