Allan T. Davidson

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transceiver system with reduced latency uncertainty
- Patent number 9,559,881
- Issue date Jan 31, 2017
- Altera Corporation
- Neville Carvalho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase detection circuit and method
- Patent number 8,334,716
- Issue date Dec 18, 2012
- Altera Corporation
- Allan Thomas Davidson
- G11 - INFORMATION STORAGE
Information Patent Grant
Differential input receiver with programmable failsafe
- Patent number 7,245,154
- Issue date Jul 17, 2007
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output impedance measurement techniques
- Patent number 7,057,397
- Issue date Jun 6, 2006
- Lattice Semiconductor Corporation
- Allan T. Davidson
- G11 - INFORMATION STORAGE
Information Patent Grant
Scalable device architecture for high-speed interfaces
- Patent number 6,903,575
- Issue date Jun 7, 2005
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable and fixed logic circuitry for high-speed interfaces
- Patent number 6,894,530
- Issue date May 17, 2005
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Package migration for related programmable logic devices
- Patent number 6,225,821
- Issue date May 1, 2001
- Lattice Semiconductor Corporation
- Allan T. Davidson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,191,609
- Issue date Feb 20, 2001
- Lattice Semiconductor Corporation
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combination of global clock and localized clocks
- Patent number 6,133,750
- Issue date Oct 17, 2000
- Lattice Semiconductor Corp.
- Albert Chan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Transceiver system with reduced latency uncertainty
- Publication number 20090161738
- Publication date Jun 25, 2009
- Altera Corporation
- Neville Carvalho
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Allan T. Davidson

Person

Patents Grantslast 30 patents

Transceiver system with reduced latency uncertainty

Digital phase detection circuit and method

Differential input receiver with programmable failsafe

Output impedance measurement techniques

Scalable device architecture for high-speed interfaces

Programmable and fixed logic circuitry for high-speed interfaces

Package migration for related programmable logic devices

Combination of global clock and localized clocks

Combination of global clock and localized clocks

Patents Applicationslast 30 patents

Transceiver system with reduced latency uncertainty