Alok Jain

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Method for mutation coverage during formal verification
- Patent number 8,990,746
- Issue date Mar 24, 2015
- Cadence Design Systems, Inc.
- Pradeep Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for debugging unreachable design targets detected by formal...
- Patent number 8,910,099
- Issue date Dec 9, 2014
- Cadence Design Systems, Inc.
- Pradeep Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System method and apparatus for vacuity detection
- Patent number 8,612,905
- Issue date Dec 17, 2013
- Cadence Design Systems, Inc.
- Pradeep Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification plans to merging design verification metrics
- Patent number 8,413,088
- Issue date Apr 2, 2013
- Cadence Design Systems, Inc.
- Frank Armbruster
- G01 - MEASURING TESTING
Information Patent Grant
Constraint minimization method for formal verification
- Patent number 8,316,332
- Issue date Nov 20, 2012
- Cadence Design Systems, Inc.
- Pradeep Goyal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
State retention for formal verification
- Patent number 7,747,971
- Issue date Jun 29, 2010
- Cadence Design Systems, Inc.
- Manu Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for verifying circuit designs through propagation...
- Patent number 7,444,274
- Issue date Oct 28, 2008
- Cadence Design Systems, Inc.
- Manu Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design optimization using approximate reachability analysis
- Patent number 7,428,712
- Issue date Sep 23, 2008
- Cadence Design Systems, Inc.
- Vinaya Kumar Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for partitioning an integrated circuit design
- Patent number 7,047,510
- Issue date May 16, 2006
- Cadence Design Systems, Inc.
- Manu Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for recognizing and abstracting memory structures
- Patent number 7,031,898
- Issue date Apr 18, 2006
- Cadence Design Systems, Inc.
- Alok Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for recognizing and abstracting pre-charged latches and f...
- Patent number 6,848,090
- Issue date Jan 25, 2005
- Cadence Design Systems, Inc.
- Alok Jain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Mechanism for recognizing and abstracting memory structures
- Publication number 20030120473
- Publication date Jun 26, 2003
- Alok Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for recognizing and abstracting pre-charged latches and f...
- Publication number 20030110458
- Publication date Jun 12, 2003
- Alok Jain
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method for mutation coverage during formal verification

Method for debugging unreachable design targets detected by formal...

System method and apparatus for vacuity detection

Verification plans to merging design verification metrics

Constraint minimization method for formal verification

State retention for formal verification

Method and system for verifying circuit designs through propagation...

Design optimization using approximate reachability analysis

Method and system for partitioning an integrated circuit design

Mechanism for recognizing and abstracting memory structures

Mechanism for recognizing and abstracting pre-charged latches and f...

Patents Applicationslast 30 patents

Mechanism for recognizing and abstracting memory structures

Mechanism for recognizing and abstracting pre-charged latches and f...