Alon Saado

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Centralized recording and processing of received packet parameters
- Patent number 8,681,786
- Issue date Mar 25, 2014
- VIA Telecom Co., Ltd.
- Qiang Shen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Canonical signed digit (CSD) coefficient multiplier with optimization
- Patent number 7,680,872
- Issue date Mar 16, 2010
- VIA Telecom Co., Ltd.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for patching for program ROM
- Patent number 7,644,223
- Issue date Jan 5, 2010
- VIA Telecom Co., Ltd.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing multiplex sublayer data unit data in hardware
- Patent number 7,613,186
- Issue date Nov 3, 2009
- VIA Telecom Co., Ltd.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Waveform generation for FM synthesis
- Patent number 7,470,849
- Issue date Dec 30, 2008
- VIA Telecom Co., Ltd.
- Alon Saado
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Method and/or architecture implemented in hardware for the adjustme...
- Patent number 7,376,152
- Issue date May 20, 2008
- VIA Telecom Co., Ltd.
- Alon Saado
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and/or apparatus implemented in hardware to discard bad logi...
- Patent number 7,340,667
- Issue date Mar 4, 2008
- VIA Telecom Co., Ltd.
- Alon Saado
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Read enable generator for a turbo decoder deinterleaved symbol memory
- Patent number 7,266,756
- Issue date Sep 4, 2007
- VIA Telecom Co., Ltd.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and/or apparatus for performing static timing analysis on a...
- Patent number 7,231,567
- Issue date Jun 12, 2007
- VIA Telecom Co., Ltd.
- Alon Saado
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for a lock detector for a phase-locked loop
- Patent number 7,157,978
- Issue date Jan 2, 2007
- Via Telecom Co., Ltd.
- Alon Saado
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and/or apparatus for generating a write gated clock signal
- Patent number 7,046,066
- Issue date May 16, 2006
- VIA Telecom Co., Ltd.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and/or method for implementing a patch mechanism for embedd...
- Patent number 6,891,765
- Issue date May 10, 2005
- Via Telecom, Inc.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CENTRALIZED RECORDING AND PROCESSING OF RECEIVED PACKET PARAMETERS
- Publication number 20110194555
- Publication date Aug 11, 2011
- VIA TELECOM, INC.
- Qiang Shen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Circuit and method for patching for program ROM
- Publication number 20080112205
- Publication date May 15, 2008
- VIA TELECOM CO., LTD.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Waveform generation for FM synthesis
- Publication number 20070079689
- Publication date Apr 12, 2007
- VIA TELECOM CO., LTD.
- Alon Saado
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Application
Method and system for a lock detector for a phase-locked loop
- Publication number 20060226914
- Publication date Oct 12, 2006
- Alon Saado
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Canonical signed digit (CSD) coefficient multiplier with optimization
- Publication number 20060155793
- Publication date Jul 13, 2006
- VIA TELECOM CO., LTD.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read enable generator for a turbo decoder deinterleaved symbol memory
- Publication number 20050289432
- Publication date Dec 29, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and/or apparatus for generating a write gated clock signal
- Publication number 20050275441
- Publication date Dec 15, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and/or apparatus implemented in hardware to discard bad logi...
- Publication number 20050251717
- Publication date Nov 10, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Processing multiplex sublayer data unit data in hardware
- Publication number 20050249204
- Publication date Nov 10, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and/or architecture implemented in hardware for the adjustme...
- Publication number 20050220151
- Publication date Oct 6, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and/or apparatus for performing static timing analysis on a...
- Publication number 20050193299
- Publication date Sep 1, 2005
- VIA TELECOM CO., LTD.
- Alon Saado
- G01 - MEASURING TESTING
Information Patent Application
Circuit and/or method for implementing a patch mechanism for embedd...
- Publication number 20050030796
- Publication date Feb 10, 2005
- VIA TELECOM, INC.
- Alon Saado
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Centralized recording and processing of received packet parameters

Canonical signed digit (CSD) coefficient multiplier with optimization

Circuit and method for patching for program ROM

Processing multiplex sublayer data unit data in hardware

Waveform generation for FM synthesis

Method and/or architecture implemented in hardware for the adjustme...

Method and/or apparatus implemented in hardware to discard bad logi...

Read enable generator for a turbo decoder deinterleaved symbol memory

Method and/or apparatus for performing static timing analysis on a...

Method and system for a lock detector for a phase-locked loop

Method and/or apparatus for generating a write gated clock signal

Circuit and/or method for implementing a patch mechanism for embedd...

Patents Applicationslast 30 patents

CENTRALIZED RECORDING AND PROCESSING OF RECEIVED PACKET PARAMETERS

Circuit and method for patching for program ROM

Waveform generation for FM synthesis

Method and system for a lock detector for a phase-locked loop

Canonical signed digit (CSD) coefficient multiplier with optimization

Read enable generator for a turbo decoder deinterleaved symbol memory

Method and/or apparatus for generating a write gated clock signal

Method and/or apparatus implemented in hardware to discard bad logi...

Processing multiplex sublayer data unit data in hardware

Method and/or architecture implemented in hardware for the adjustme...

Method and/or apparatus for performing static timing analysis on a...

Circuit and/or method for implementing a patch mechanism for embedd...