Aman Gayasen

Person

Hyderabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Synthesis flow for data processing engine array applications relyin...
- Patent number 11,829,733
- Issue date Nov 28, 2023
- Xilinx, Inc.
- Sumanta Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compaction of multiplier and adder circuits
- Patent number 11,768,663
- Issue date Sep 26, 2023
- Xilinx, Inc.
- Srijan Tiwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data flow graph refinement using range set information for improved...
- Patent number 11,755,801
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Kishore Vedavyasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visualization of data buses in circuit designs
- Patent number 11,586,791
- Issue date Feb 21, 2023
- Xilinx, Inc.
- Anup Hosangadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data flow graph optimization techniques for RTL loops with conditio...
- Patent number 10,943,042
- Issue date Mar 9, 2021
- Xilinx, Inc.
- Sumanta Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization-aware incremental synthesis
- Patent number 10,839,118
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Kameshwar Chandrasekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Folding multiply-and-accumulate logic
- Patent number 10,789,401
- Issue date Sep 29, 2020
- Xilinx, Inc.
- Srijan Tiwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental synthesis for changes to a circuit design
- Patent number 10,586,005
- Issue date Mar 10, 2020
- Xilinx, Inc.
- Kameshwar Chandrasekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying data flow graphs using range information
- Patent number 10,534,885
- Issue date Jan 14, 2020
- Xilinx, Inc.
- Sumanta Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loop optimization for implementing circuit designs in hardware
- Patent number 10,331,836
- Issue date Jun 25, 2019
- Xilinx, Inc.
- Anup Hosangadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelizing timing-based operations for circuit designs
- Patent number 10,303,833
- Issue date May 28, 2019
- Xilinx, Inc.
- Aman Gayasen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical optimization for timing closure for an integrated circuit
- Patent number 8,984,462
- Issue date Mar 17, 2015
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ALIGNMENT OF MACROS BASED ON ANCHOR LOCATIONS
- Publication number 20240193341
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Veeresh Pratap Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIS FOR MATRIX MULTIPLICATION USING A DATA PROCESSING ARRAY
- Publication number 20240193225
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Srijan Tiwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIS FLOW FOR DATA PROCESSING ENGINE ARRAY APPLICATIONS RELYIN...
- Publication number 20230161569
- Publication date May 25, 2023
- Xilinx, Inc.
- Sumanta Datta
- G06 - COMPUTING CALCULATING COUNTING

Aman Gayasen

Person

Patents Grantslast 30 patents

Synthesis flow for data processing engine array applications relyin...

Compaction of multiplier and adder circuits

Data flow graph refinement using range set information for improved...

Visualization of data buses in circuit designs

Data flow graph optimization techniques for RTL loops with conditio...

Optimization-aware incremental synthesis

Folding multiply-and-accumulate logic

Incremental synthesis for changes to a circuit design

Modifying data flow graphs using range information

Loop optimization for implementing circuit designs in hardware

Parallelizing timing-based operations for circuit designs

Physical optimization for timing closure for an integrated circuit

Patents Applicationslast 30 patents

ALIGNMENT OF MACROS BASED ON ANCHOR LOCATIONS

SYNTHESIS FOR MATRIX MULTIPLICATION USING A DATA PROCESSING ARRAY

SYNTHESIS FLOW FOR DATA PROCESSING ENGINE ARRAY APPLICATIONS RELYIN...