Amar Amin

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Milpitas, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods for avoiding parasitic capacitance in an integrated circuit...
- Patent number 8,288,269
- Issue date Oct 16, 2012
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package and method using isolated VSS plane to accomm...
- Patent number 8,129,759
- Issue date Mar 6, 2012
- LSI Logic Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device for avoiding parasitic capacitance in an integrated circuit...
- Patent number 8,049,340
- Issue date Nov 1, 2011
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wire bond integrated circuit package for high speed I/O
- Patent number 7,804,167
- Issue date Sep 28, 2010
- LSI Logic Corporation
- Clifford Fishley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package and method using isolated Vss plane to accomm...
- Patent number 7,646,091
- Issue date Jan 12, 2010
- LSI Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Methods for Avoiding Parasitic Capacitance in an Integrated Circuit...
- Publication number 20120021599
- Publication date Jan 26, 2012
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMM...
- Publication number 20100067207
- Publication date Mar 18, 2010
- LSI Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O
- Publication number 20080128919
- Publication date Jun 5, 2008
- Clifford Fishley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package and method using isolated Vss plane to accomm...
- Publication number 20070235849
- Publication date Oct 11, 2007
- LSI Logic Corporation
- Maurice O. Othieno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT...
- Publication number 20070222084
- Publication date Sep 27, 2007
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR