Amit CHHABRA

Person

Greater Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-bitcell structure with shared read port
- Patent number 12,165,737
- Issue date Dec 10, 2024
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture
- Patent number 12,052,860
- Issue date Jul 30, 2024
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-transistor stack architecture in a single vertical stack
- Patent number 12,040,232
- Issue date Jul 16, 2024
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-transistor stack bitcell architecture
- Patent number 12,035,517
- Issue date Jul 9, 2024
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bitcell architecture
- Patent number 11,895,816
- Issue date Feb 6, 2024
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sensor for performance variation of memory read and write character...
- Patent number 11,742,051
- Issue date Aug 29, 2023
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming multi-stack transistors in a single semiconductor...
- Patent number 11,495,499
- Issue date Nov 8, 2022
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage retention techniques
- Patent number 11,114,154
- Issue date Sep 7, 2021
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensor for performance variation of memory read and write character...
- Patent number 11,069,424
- Issue date Jul 20, 2021
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Ring oscillator based bitcell delay monitor
- Patent number 10,964,379
- Issue date Mar 30, 2021
- ARM Limited
- Rainer Herberholz
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault detection circuitry
- Patent number 10,848,186
- Issue date Nov 24, 2020
- ARM Limited
- Vivek Asthana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-timed memory with adaptive voltage scaling
- Patent number 10,839,865
- Issue date Nov 17, 2020
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Transient sensing circuitry
- Patent number 10,715,148
- Issue date Jul 14, 2020
- ARM Limited
- Rainer Herberholz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for automatic detection of power up for a dual-ra...
- Patent number 9,728,232
- Issue date Aug 8, 2017
- STMicroelectronics International N.V.
- Amit Chhabra
- G05 - CONTROLLING REGULATING
Information Patent Grant
Body bias multiplexer for stress-free transmission of positive and...
- Patent number 9,659,933
- Issue date May 23, 2017
- STMicroelectronics International N.V.
- Vikas Rana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra-low voltage temperature threshold detector
- Patent number 9,559,665
- Issue date Jan 31, 2017
- STMicroelectronics International N.V.
- Amit Chhabra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for improving memory performance and identifying...
- Patent number 9,543,044
- Issue date Jan 10, 2017
- STMicroelectronics International N.V.
- Abhishek Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-supply dual port register file
- Patent number 9,396,790
- Issue date Jul 19, 2016
- STMicroelectronics International N.V.
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of minimizing the operating voltage of an SRAM cell
- Patent number 9,390,786
- Issue date Jul 12, 2016
- STMicroelectronics S.A.
- Christophe Lecocq
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for automatic detection of power up for a dual-ra...
- Patent number 9,378,779
- Issue date Jun 28, 2016
- STMicroelectronics International N.V.
- Amit Chhabra
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for testing of a memory with redundancy elements
- Patent number 8,458,545
- Issue date Jun 4, 2013
- STMicroelectronics International N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for testing shadow logic
- Patent number 8,381,049
- Issue date Feb 19, 2013
- STMicroelectronics International N.V.
- Amit Chhabra
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Calibration Techniques for Temperature Sensors
- Publication number 20250137855
- Publication date May 1, 2025
- ARM Limited
- Tirdad Anthony Takeshian
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF MONITORING A CLOCK SIGNAL
- Publication number 20250138577
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE DROOP DETECTION
- Publication number 20250138059
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUIT FOR MONITORING VOLTAGE DROOP RESPONSE
- Publication number 20250138061
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS FOR SYSTEM CLOCK CONTROL
- Publication number 20250138573
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUITRY FOR DETERMINING SYSTEM CHARACTERISTICS OF AN E...
- Publication number 20250141440
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Temperature and Voltage Profiling Computer Systems and Methods
- Publication number 20250139309
- Publication date May 1, 2025
- ARM Limited
- Rainer Herberholz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF MONITORING OPERATING PARAMETERS
- Publication number 20250138611
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DROOP PROTECTION METHOD AND CIRCUIT
- Publication number 20250138615
- Publication date May 1, 2025
- ARM Limited
- Rainer Herberholz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DROOP PROTECTION METHOD AND CIRCUIT
- Publication number 20250141436
- Publication date May 1, 2025
- ARM Limited
- Rainer Herberholz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVALUATING PERFORMANCE OF A DROOP MITIGATION SCHEME
- Publication number 20250141438
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK CONTROL SCHEME, METHODS AND CIRCUITS THEREFOR
- Publication number 20250138572
- Publication date May 1, 2025
- ARM Limited
- Amit Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Stack Bitcell Architecture
- Publication number 20240260261
- Publication date Aug 1, 2024
- ARM Limited
- Yannick Marc Nevers
Information Patent Application
Circuit Architecture in Multi-Dimensional Monolithic Structure
- Publication number 20230335537
- Publication date Oct 19, 2023
- ARM Limited
- Lokesh Kumar Saini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Device Stack Structure
- Publication number 20230317717
- Publication date Oct 5, 2023
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Bitcell Structure with Shared Read Port
- Publication number 20230282253
- Publication date Sep 7, 2023
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Transistor Stack Architecture
- Publication number 20230118510
- Publication date Apr 20, 2023
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Architecture
- Publication number 20220223610
- Publication date Jul 14, 2022
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Transistor Stack Architecture
- Publication number 20220199471
- Publication date Jun 23, 2022
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Transistor Stack Bitcell Architecture
- Publication number 20220199629
- Publication date Jun 23, 2022
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bitcell Architecture
- Publication number 20220181331
- Publication date Jun 9, 2022
- ARM Limited
- Amit Chhabra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sensor for Performance Variation of Memory Read and Write Character...
- Publication number 20210343359
- Publication date Nov 4, 2021
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage Retention Techniques
- Publication number 20210183436
- Publication date Jun 17, 2021
- ARM Limited
- Amit Chhabra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Self-Timed Memory with Adaptive Voltage Scaling
- Publication number 20200342916
- Publication date Oct 29, 2020
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
Sensor for Performance Variation of Memory Read and Write Character...
- Publication number 20200143901
- Publication date May 7, 2020
- ARM Limited
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
Ring Oscillator Based Bitcell Delay Monitor
- Publication number 20200143873
- Publication date May 7, 2020
- ARM Limited
- Rainer Herberholz
- G11 - INFORMATION STORAGE
Information Patent Application
Fault Detection Circuitry
- Publication number 20190253084
- Publication date Aug 15, 2019
- ARM Limited
- Vivek Asthana
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA-LOW VOLTAGE TEMPERATURE THRESHOLD DETECTOR
- Publication number 20170005641
- Publication date Jan 5, 2017
- STMicroelectronics International N.V.
- Amit Chhabra
- G11 - INFORMATION STORAGE
Information Patent Application
BODY BIAS MULTIPLEXER FOR STRESS-FREE TRANSMISSION OF POSITIVE AND...
- Publication number 20160315611
- Publication date Oct 27, 2016
- STMicroelectronics International N.V.
- Vikas RANA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RA...
- Publication number 20160275999
- Publication date Sep 22, 2016
- STMicroelectronics International N.V
- Amit Chhabra
- G11 - INFORMATION STORAGE

Amit CHHABRA

Person

Patents Grantslast 30 patents

Multi-bitcell structure with shared read port

Memory architecture

Multi-transistor stack architecture in a single vertical stack

Multi-transistor stack bitcell architecture

Bitcell architecture

Sensor for performance variation of memory read and write character...

Method of forming multi-stack transistors in a single semiconductor...

Voltage retention techniques

Sensor for performance variation of memory read and write character...

Ring oscillator based bitcell delay monitor

Fault detection circuitry

Self-timed memory with adaptive voltage scaling

Transient sensing circuitry

System and method for automatic detection of power up for a dual-ra...

Body bias multiplexer for stress-free transmission of positive and...

Ultra-low voltage temperature threshold detector

System and method for improving memory performance and identifying...

Multi-supply dual port register file

Method of minimizing the operating voltage of an SRAM cell

System and method for automatic detection of power up for a dual-ra...

Method and apparatus for testing of a memory with redundancy elements

Apparatus and method for testing shadow logic

Patents Applicationslast 30 patents

Calibration Techniques for Temperature Sensors

METHOD OF MONITORING A CLOCK SIGNAL

VOLTAGE DROOP DETECTION

METHOD AND CIRCUIT FOR MONITORING VOLTAGE DROOP RESPONSE

METHODS AND APPARATUS FOR SYSTEM CLOCK CONTROL

METHOD AND CIRCUITRY FOR DETERMINING SYSTEM CHARACTERISTICS OF AN E...

Temperature and Voltage Profiling Computer Systems and Methods

METHOD OF MONITORING OPERATING PARAMETERS

DROOP PROTECTION METHOD AND CIRCUIT

DROOP PROTECTION METHOD AND CIRCUIT

EVALUATING PERFORMANCE OF A DROOP MITIGATION SCHEME

CLOCK CONTROL SCHEME, METHODS AND CIRCUITS THEREFOR

Multi-Stack Bitcell Architecture

Circuit Architecture in Multi-Dimensional Monolithic Structure

Multi-Device Stack Structure

Multi-Bitcell Structure with Shared Read Port

Multi-Transistor Stack Architecture

Memory Architecture

Multi-Transistor Stack Architecture

Multi-Transistor Stack Bitcell Architecture

Bitcell Architecture

Sensor for Performance Variation of Memory Read and Write Character...

Voltage Retention Techniques

Self-Timed Memory with Adaptive Voltage Scaling

Sensor for Performance Variation of Memory Read and Write Character...

Ring Oscillator Based Bitcell Delay Monitor

Fault Detection Circuitry

ULTRA-LOW VOLTAGE TEMPERATURE THRESHOLD DETECTOR

BODY BIAS MULTIPLEXER FOR STRESS-FREE TRANSMISSION OF POSITIVE AND...

SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RA...