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Amit Dhuria
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Cupertino, CA, US
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last 30 patents
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Patent Grant
Method, system, and product for deferred merge based method for gra...
Patent number
11,188,696
Issue date
Nov 30, 2021
Cadence Design Systems, Inc.
Amit Dhuria
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method, system, and product for an improved approach to placement a...
Patent number
11,144,698
Issue date
Oct 12, 2021
Cadence Design Systems, Inc.
Vibhor Garg
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Deterministic loop breaking in multi-mode multi-corner static timin...
Patent number
11,003,821
Issue date
May 11, 2021
Cadence Design Systems, Inc.
Sri Harsha Pothukuchi
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Shared timing graph propagation for multi-mode multi-corner static...
Patent number
10,990,733
Issue date
Apr 27, 2021
Cadence Design Systems, Inc.
Vibhor Garg
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Timing context generation with multi-instance blocks for hierarchic...
Patent number
10,169,501
Issue date
Jan 1, 2019
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Methods, systems, and articles of manufacture for multi-mode, multi...
Patent number
10,133,842
Issue date
Nov 20, 2018
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Hierarchical timing analysis for multi-instance blocks
Patent number
10,037,394
Issue date
Jul 31, 2018
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING