Amit PATANKAR

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
System level simulation in Network on Chip architecture
- Patent number 10,496,770
- Issue date Dec 3, 2019
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System level simulation in network on chip architecture
- Patent number 9,471,726
- Issue date Oct 18, 2016
- NetSpeed Systems
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic NoC topology generation
- Patent number 9,054,977
- Issue date Jun 9, 2015
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM LEVEL SIMULATION IN NETWORK ON CHIP ARCHITECTURE
- Publication number 20170061053
- Publication date Mar 2, 2017
- NETSPEED SYSTEMS
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC NoC TOPOLOGY GENERATION
- Publication number 20150036536
- Publication date Feb 5, 2015
- NETSPEED SYSTEMS
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM LEVEL SIMULATION IN NETWORK ON CHIP ARCHITECTURE
- Publication number 20150032437
- Publication date Jan 29, 2015
- NETSPEED SYSTEMS
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING