Amitava Majumdar

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Intra-chip and inter-chip data protection
- Patent number 12,105,658
- Issue date Oct 1, 2024
- Xilinx, Inc.
- Pramod Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip testing interface with reduced signal wires
- Patent number 11,860,228
- Issue date Jan 2, 2024
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid synchronous and asynchronous control for scan-based testing
- Patent number 11,755,804
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Runtime measurement of process variations and supply voltage charac...
- Patent number 11,585,854
- Issue date Feb 21, 2023
- Xilinx, Inc.
- Da Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing memory elements using an internal testing interface
- Patent number 11,500,017
- Issue date Nov 15, 2022
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Restoring memory data integrity
- Patent number 11,429,481
- Issue date Aug 30, 2022
- Xilinx, Inc.
- Sarosh I. Azad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable dynamic clock stretch for at-speed debugging of integr...
- Patent number 11,290,095
- Issue date Mar 29, 2022
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit architecture for expanded design for testability functionality
- Patent number 11,263,377
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit skew determination
- Patent number 10,756,711
- Issue date Aug 25, 2020
- Xilinx, Inc.
- Amitava Majumdar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Breakpointing circuitry that evaluates breakpoint conditions while...
- Patent number 10,754,759
- Issue date Aug 25, 2020
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data unit breakpointing circuits and methods
- Patent number 10,621,067
- Issue date Apr 14, 2020
- Xilinx, Inc.
- Georgios Tzimpragos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient system debug infrastructure for tiled architecture
- Patent number 10,110,234
- Issue date Oct 23, 2018
- Xilinx, Inc.
- Uma E. Durairajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing interposer dies prior to assembly
- Patent number 9,989,572
- Issue date Jun 5, 2018
- Xilinx, Inc.
- Raghunandan Chaware
- G01 - MEASURING TESTING
Information Patent Grant
Heterogeneous integration of integrated circuit device and companio...
- Patent number 9,865,567
- Issue date Jan 9, 2018
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuits for and methods of implementing a design for testing and d...
- Patent number 9,798,352
- Issue date Oct 24, 2017
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer-less stack die interconnect
- Patent number 9,761,533
- Issue date Sep 12, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock stoppage in integrated circuits with multiple asynchronous cl...
- Patent number 9,600,018
- Issue date Mar 21, 2017
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits for and methods of testing the operation of an input/outpu...
- Patent number 9,500,700
- Issue date Nov 22, 2016
- Xilinx, Inc.
- Xiaobao Wang
- G01 - MEASURING TESTING
Information Patent Grant
Testing for shorts between internal nodes of a power distribution grid
- Patent number 9,453,870
- Issue date Sep 27, 2016
- Xilinx, Inc.
- Amitava Majumdar
- G01 - MEASURING TESTING
Information Patent Grant
Time-to-digital conversion
- Patent number 8,884,804
- Issue date Nov 11, 2014
- Xilinx, Inc.
- Amitava Majumdar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for AC scan testing with distributed capture a...
- Patent number 8,407,544
- Issue date Mar 26, 2013
- Advanced Micro Devices, Inc.
- Amitava Majumdar
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test (BIST) of memory interconnect
- Patent number 7,096,393
- Issue date Aug 22, 2006
- Sun Microsystems, Inc.
- Olivier Caty
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for generating and verifying libraries for ATP...
- Patent number 7,065,724
- Issue date Jun 20, 2006
- Sun Microsystems, Inc.
- Olivier Caty
- G01 - MEASURING TESTING
Information Patent Grant
Instruction-based built-in self-test (BIST) of external memory
- Patent number 7,020,820
- Issue date Mar 28, 2006
- Sun Microsystems, Inc.
- Olivier Caty
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic generation and validation of memory test models
- Patent number 6,813,201
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Kamran Zarrineh
- G11 - INFORMATION STORAGE
Information Patent Grant
Spatial and temporal alignment of a scan dump for debug of scan-bas...
- Patent number 6,507,925
- Issue date Jan 14, 2003
- Sun Microsystems, Inc.
- Sridhar Narayanan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DFxNoC - A MULTI-PROTOCOL, MULTI-CAST, AND MULTI-ROOT NETWORK-ON-CH...
- Publication number 20240356544
- Publication date Oct 24, 2024
- Xilinx, Inc.
- Rambabu NERUKONDA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
- Publication number 20230366929
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Albert Shih-Huai LIN
- G01 - MEASURING TESTING
Information Patent Application
FLEXIBLE QUEUE PROVISIONING FOR PARTITIONED ACCELERATION DEVICE
- Publication number 20230290189
- Publication date Sep 14, 2023
- Xilinx, Inc.
- Yanran CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING
- Publication number 20230205959
- Publication date Jun 29, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTRA-CHIP AND INTER-CHIP DATA PROTECTION
- Publication number 20230085149
- Publication date Mar 16, 2023
- Xilinx, Inc.
- Pramod BHARDWAJ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPOSER-LESS STACK DIE INTERCONNECT
- Publication number 20170110407
- Publication date Apr 20, 2017
- Xilinx, Inc.
- Raghunandan Chaware
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Logic Content Processing for Hardware Acceleration of Multi-Pattern...
- Publication number 20140019486
- Publication date Jan 16, 2014
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR AC SCAN TESTING WITH DISTRIBUTED CAPTURE A...
- Publication number 20110258505
- Publication date Oct 20, 2011
- Amitava Majumdar
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for generating and verifying libraries for ATP...
- Publication number 20040143783
- Publication date Jul 22, 2004
- Sun Microsystems, Inc., a Delaware Corporation
- Olivier Caty
- G01 - MEASURING TESTING
Information Patent Application
Built-in self-test (BIST) of memory interconnect
- Publication number 20040123192
- Publication date Jun 24, 2004
- Olivier Caty
- G11 - INFORMATION STORAGE
Information Patent Application
Instruction-based built-in self-test (BIST) of external memory
- Publication number 20040123200
- Publication date Jun 24, 2004
- Olivier Caty
- G01 - MEASURING TESTING
Information Patent Application
Method for transforming stand-alone verification tests for an embed...
- Publication number 20030171906
- Publication date Sep 11, 2003
- Ishwardutt Parulkar
- G01 - MEASURING TESTING
Information Patent Application
Automatic generation and validation of memory test models
- Publication number 20030076723
- Publication date Apr 24, 2003
- SUN MICROSYSTEMS, INC.
- Kamran Zarrineh
- G11 - INFORMATION STORAGE

Amitava Majumdar

Person

Patents Grantslast 30 patents

Intra-chip and inter-chip data protection

Integrated circuit chip testing interface with reduced signal wires

Hybrid synchronous and asynchronous control for scan-based testing

Scalable scan architecture for multi-circuit block arrays

Runtime measurement of process variations and supply voltage charac...

Testing memory elements using an internal testing interface

Restoring memory data integrity

Programmable dynamic clock stretch for at-speed debugging of integr...

Circuit architecture for expanded design for testability functionality

Test circuits for testing a die stack

Integrated circuit skew determination

Breakpointing circuitry that evaluates breakpoint conditions while...

Data unit breakpointing circuits and methods

Efficient system debug infrastructure for tiled architecture

Method and apparatus for testing interposer dies prior to assembly

Heterogeneous integration of integrated circuit device and companio...

Circuits for and methods of implementing a design for testing and d...

Interposer-less stack die interconnect

Clock stoppage in integrated circuits with multiple asynchronous cl...

Circuits for and methods of testing the operation of an input/outpu...

Testing for shorts between internal nodes of a power distribution grid

Time-to-digital conversion

Method and apparatus for AC scan testing with distributed capture a...

Built-in self-test (BIST) of memory interconnect

Method and apparatus for generating and verifying libraries for ATP...

Instruction-based built-in self-test (BIST) of external memory

Automatic generation and validation of memory test models

Spatial and temporal alignment of a scan dump for debug of scan-bas...

Patents Applicationslast 30 patents

DFxNoC - A MULTI-PROTOCOL, MULTI-CAST, AND MULTI-ROOT NETWORK-ON-CH...

INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES

FLEXIBLE QUEUE PROVISIONING FOR PARTITIONED ACCELERATION DEVICE

HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING

INTRA-CHIP AND INTER-CHIP DATA PROTECTION

INTERPOSER-LESS STACK DIE INTERCONNECT

Logic Content Processing for Hardware Acceleration of Multi-Pattern...

METHOD AND APPARATUS FOR AC SCAN TESTING WITH DISTRIBUTED CAPTURE A...

Method and apparatus for generating and verifying libraries for ATP...

Built-in self-test (BIST) of memory interconnect

Instruction-based built-in self-test (BIST) of external memory

Method for transforming stand-alone verification tests for an embed...

Automatic generation and validation of memory test models