Amruthavalli P. Alur

Person

Tempe, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package-integrated multi-turn coil embedded in a package magnetic core
- Patent number 11,955,426
- Issue date Apr 9, 2024
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,935,805
- Issue date Mar 19, 2024
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid microelectronic substrates
- Patent number 11,923,257
- Issue date Mar 5, 2024
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stripped redistrubution-layer fabrication for package-top embedded...
- Patent number 11,908,793
- Issue date Feb 20, 2024
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device with embedded die substrate on interposer
- Patent number 11,894,311
- Issue date Feb 6, 2024
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded multi-die interconnect bridge packages with lithographical...
- Patent number 11,764,158
- Issue date Sep 19, 2023
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die cavity package
- Patent number 11,705,377
- Issue date Jul 18, 2023
- Intel Corporation
- Mitul Modi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via-in-via structure for high density package integrated inductor
- Patent number 11,676,950
- Issue date Jun 13, 2023
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,664,290
- Issue date May 30, 2023
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stripped redistrubution-layer fabrication for package-top embedded...
- Patent number 11,658,111
- Issue date May 23, 2023
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to pattern TFC and incorporation in the ODI architecture an...
- Patent number 11,581,271
- Issue date Feb 14, 2023
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate patch reconstitution options
- Patent number 11,552,019
- Issue date Jan 10, 2023
- Intel Corporation
- Haifa Hariri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer solution based deposition of dielectrics for advanced s...
- Patent number 11,508,636
- Issue date Nov 22, 2022
- Intel Corporation
- Andrew Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin, hyper-density semiconductor packages
- Patent number 11,430,724
- Issue date Aug 30, 2022
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device with embedded die substrate on interposer
- Patent number 11,430,740
- Issue date Aug 30, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer embedded magnetic inductor coil
- Patent number 11,404,364
- Issue date Aug 2, 2022
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-integrated multi-turn coil embedded in a package magnetic core
- Patent number 11,393,751
- Issue date Jul 19, 2022
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die cavity package
- Patent number 11,328,968
- Issue date May 10, 2022
- Intel Corporation
- Mitul Modi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus with embedded fine line space in a cavity, and a method f...
- Patent number 11,272,619
- Issue date Mar 8, 2022
- Intel Corporation
- Kristof Darmawikarta
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,158,558
- Issue date Oct 26, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid microelectronic substrates
- Patent number 11,114,353
- Issue date Sep 7, 2021
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pseudo-stripline using double solder-resist structure
- Patent number 11,107,780
- Issue date Aug 31, 2021
- Intel Corporation
- Lilia May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate having polymer-derived ceramic core
- Patent number 11,075,130
- Issue date Jul 27, 2021
- Intel Corporation
- Lisa Ying Ying Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded multi-die interconnect bridge packages with lithotgraphica...
- Patent number 11,043,457
- Issue date Jun 22, 2021
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stripped redistrubution-layer fabrication for package-top embedded...
- Patent number 10,998,262
- Issue date May 4, 2021
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric electronic substrate and method of manufacture
- Patent number 10,980,129
- Issue date Apr 13, 2021
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Plated through hole socketing coupled to a solder ball to engage wi...
- Patent number 10,741,947
- Issue date Aug 11, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-packaging for single-socketing
- Patent number 10,734,358
- Issue date Aug 4, 2020
- Intel Corporation
- Jonathan L. Rosch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded multi-die interconnect bridge packages with lithographical...
- Patent number 10,707,168
- Issue date Jul 7, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric electronic substrate and method of manufacture
- Patent number 10,624,213
- Issue date Apr 14, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...
- Publication number 20240136278
- Publication date Apr 25, 2024
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20240030116
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20230245940
- Publication date Aug 3, 2023
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20230138543
- Publication date May 4, 2023
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20220344247
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-INTEGRATED MULTI-TURN COIL EMBEDDED IN A PACKAGE MAGNETIC CORE
- Publication number 20220310512
- Publication date Sep 29, 2022
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DIE CAVITY PACKAGE
- Publication number 20220238402
- Publication date Jul 28, 2022
- Intel Corporation
- Mitul MODI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER
- Publication number 20220230965
- Publication date Jul 21, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...
- Publication number 20220230958
- Publication date Jul 21, 2022
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS WITH EMBEDDED FINE LINE SPACE IN A CAVITY, AND A METHOD F...
- Publication number 20220183157
- Publication date Jun 9, 2022
- Intel Corporation
- Kristof Darmawikarta
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER
- Publication number 20220108957
- Publication date Apr 7, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210391232
- Publication date Dec 16, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID MICROELECTRONIC SUBSTRATES
- Publication number 20210384094
- Publication date Dec 9, 2021
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AN APPARATUS WITH EMBEDDED FINE LINE SPACE IN A CAVITY, AND A METHO...
- Publication number 20210307172
- Publication date Sep 30, 2021
- Intel Corporation
- Kristof Darmawikarta
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROELECTRONIC PACKAGE WITH SUBSTRATE CAVITY FOR BRIDGE-ATTACH
- Publication number 20210272905
- Publication date Sep 2, 2021
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICA...
- Publication number 20210257303
- Publication date Aug 19, 2021
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...
- Publication number 20210202380
- Publication date Jul 1, 2021
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210111088
- Publication date Apr 15, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA-IN-VIA STRUCTURE FOR HIGH DENSITY PACKAGE INTEGRATED INDUCTOR
- Publication number 20210098436
- Publication date Apr 1, 2021
- Intel Corporation
- Krishna Bharath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE FOR AN ELECTRONIC DEVICE
- Publication number 20200411413
- Publication date Dec 31, 2020
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PSEUDO-STRIPLINE USING DOUBLE SOLDER-RESIST STRUCTURE
- Publication number 20200388582
- Publication date Dec 10, 2020
- Intel Corporation
- Lilia May
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...
- Publication number 20200328151
- Publication date Oct 15, 2020
- Intel Corporation
- Jiun Hann Sir
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICA...
- Publication number 20200303310
- Publication date Sep 24, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE PATCH RECONSTITUTION OPTIONS
- Publication number 20200294920
- Publication date Sep 17, 2020
- Intel Corporation
- Haifa HARIRI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS TO PATTERN TFC AND INCORPORATION IN THE ODI ARCHITECTURE AN...
- Publication number 20200294938
- Publication date Sep 17, 2020
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20200273784
- Publication date Aug 27, 2020
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC ELECTRONIC SUBSTRATE AND METHOD OF MANUFACTURE
- Publication number 20200221577
- Publication date Jul 9, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STACKED DIE CAVITY PACKAGE
- Publication number 20200185289
- Publication date Jun 11, 2020
- Intel Corporation
- Mitul MODI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL
- Publication number 20200066627
- Publication date Feb 27, 2020
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-INTEGRATED MULTI-TURN COIL EMBEDDED IN A PACKAGE MAGNETIC CORE
- Publication number 20200066634
- Publication date Feb 27, 2020
- Intel Corporation
- Huong Do
- H01 - BASIC ELECTRIC ELEMENTS

Amruthavalli P. Alur

Person

Patents Grantslast 30 patents

Package-integrated multi-turn coil embedded in a package magnetic core

Package with underfill containment barrier

Hybrid microelectronic substrates

Stripped redistrubution-layer fabrication for package-top embedded...

Microelectronic device with embedded die substrate on interposer

Embedded multi-die interconnect bridge packages with lithographical...

Stacked die cavity package

Via-in-via structure for high density package integrated inductor

Package with underfill containment barrier

Stripped redistrubution-layer fabrication for package-top embedded...

Methods to pattern TFC and incorporation in the ODI architecture an...

Substrate patch reconstitution options

Multi-layer solution based deposition of dielectrics for advanced s...

Ultra-thin, hyper-density semiconductor packages

Microelectronic device with embedded die substrate on interposer

Multi-layer embedded magnetic inductor coil

Package-integrated multi-turn coil embedded in a package magnetic core

Stacked die cavity package

Apparatus with embedded fine line space in a cavity, and a method f...

Package with underfill containment barrier

Hybrid microelectronic substrates

Pseudo-stripline using double solder-resist structure

Package substrate having polymer-derived ceramic core

Embedded multi-die interconnect bridge packages with lithotgraphica...

Stripped redistrubution-layer fabrication for package-top embedded...

Asymmetric electronic substrate and method of manufacture

Plated through hole socketing coupled to a solder ball to engage wi...

Multi-packaging for single-socketing

Embedded multi-die interconnect bridge packages with lithographical...

Asymmetric electronic substrate and method of manufacture

Patents Applicationslast 30 patents

STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

PACKAGE-INTEGRATED MULTI-TURN COIL EMBEDDED IN A PACKAGE MAGNETIC CORE

STACKED DIE CAVITY PACKAGE

MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER

STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...

APPARATUS WITH EMBEDDED FINE LINE SPACE IN A CAVITY, AND A METHOD F...

MICROELECTRONIC DEVICE WITH EMBEDDED DIE SUBSTRATE ON INTERPOSER

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

HYBRID MICROELECTRONIC SUBSTRATES

AN APPARATUS WITH EMBEDDED FINE LINE SPACE IN A CAVITY, AND A METHO...

MICROELECTRONIC PACKAGE WITH SUBSTRATE CAVITY FOR BRIDGE-ATTACH

EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICA...

STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

VIA-IN-VIA STRUCTURE FOR HIGH DENSITY PACKAGE INTEGRATED INDUCTOR

SUBSTRATE FOR AN ELECTRONIC DEVICE

PSEUDO-STRIPLINE USING DOUBLE SOLDER-RESIST STRUCTURE

STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED...

EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICA...

SUBSTRATE PATCH RECONSTITUTION OPTIONS

METHODS TO PATTERN TFC AND INCORPORATION IN THE ODI ARCHITECTURE AN...

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

ASYMMETRIC ELECTRONIC SUBSTRATE AND METHOD OF MANUFACTURE

STACKED DIE CAVITY PACKAGE

MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL

PACKAGE-INTEGRATED MULTI-TURN COIL EMBEDDED IN A PACKAGE MAGNETIC CORE