Anand Rajaram

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Clock network power estimation for logical designs
- Patent number 11,526,642
- Issue date Dec 13, 2022
- Synopsys, Inc.
- Min Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis based on computing critical clock latency prob...
- Patent number 10,073,944
- Issue date Sep 11, 2018
- Synopsys, Inc.
- Anand K. Rajaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic synthesis of complex clock systems
- Patent number 9,058,451
- Issue date Jun 16, 2015
- Synopsys, Inc.
- Tao Lin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOGIC CELL PLACEMENT MECHANISMS FOR IMPROVED CLOCK ON-CHIP VARIATION
- Publication number 20240296274
- Publication date Sep 5, 2024
- NVIDIA Corp.
- Anand Kumar Rajaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT AWARE CLOCK TREE SYNTHESIS
- Publication number 20170357746
- Publication date Dec 14, 2017
- Synopsys, Inc.
- Anand K. Rajaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC SYNTHESIS OF COMPLEX CLOCK SYSTEMS
- Publication number 20140258964
- Publication date Sep 11, 2014
- Synopsys, Inc.
- Tao Lin
- G06 - COMPUTING CALCULATING COUNTING