Anatoly Koyfman

Person

Kiriat Yam, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Diminution of test templates in test suites
- Patent number 11,023,366
- Issue date Jun 1, 2021
- International Business Machines Corporation
- Samuel Solomon Ackerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation stimuli generation for post-silicon functional...
- Patent number 10,026,500
- Issue date Jul 17, 2018
- International Business Machines Corporation
- Shai Doron
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit modification
- Patent number 9,633,155
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Wesam Ibraheem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mutations on input for test generation
- Patent number 8,938,646
- Issue date Jan 20, 2015
- International Business Machines Corporation
- Laurent Fournier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for post-silicon testing
- Patent number 8,892,386
- Issue date Nov 18, 2014
- International Business Machines Corporation
- Allon Adir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction-by-instruction checking on acceleration platforms
- Patent number 8,601,418
- Issue date Dec 3, 2013
- International Business Machines Corporation
- Debapriya Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of speculative execution
- Patent number 8,589,892
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Laurent Fournier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of verification of address translation mechanisms
- Patent number 8,245,164
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Yoav Avraham Katz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling language and method for address translation design mechani...
- Patent number 7,370,296
- Issue date May 6, 2008
- International Business Machines Corporation
- Anatoly Koyfman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of mask-constrained floating-point addition and subtract...
- Patent number 7,028,067
- Issue date Apr 11, 2006
- International Business Machines Corporation
- Ziv Abraham
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DIMINUTION OF TEST TEMPLATES IN TEST SUITES
- Publication number 20210124676
- Publication date Apr 29, 2021
- International Business Machines Corporation
- Samuel Solomon Ackerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS TRANSLATION STIMULI GENERATION FOR POST-SILICON FUNCTIONAL...
- Publication number 20170140839
- Publication date May 18, 2017
- International Business Machines Corporation
- Shai Doron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT MODIFICATION
- Publication number 20170132346
- Publication date May 11, 2017
- International Business Machines Corporation
- WESAM IBRAHEEM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mutations on input for test generation
- Publication number 20140115396
- Publication date Apr 24, 2014
- Laurent Fournier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partial Instruction-by-instruction checking on acceleration platforms
- Publication number 20140019929
- Publication date Jan 16, 2014
- International Business Machines Corporation
- Gal Raviv
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION-BY-INSTRUCTION CHECKING ON ACCELERATION PLATFORMS
- Publication number 20130311962
- Publication date Nov 21, 2013
- International Business Machines Corporation
- Debapriya Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR POST-SILICON TESTING
- Publication number 20130013246
- Publication date Jan 10, 2013
- International Business Machines Corporation
- Allon Adir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION OF SPECULATIVE EXECUTION
- Publication number 20120131386
- Publication date May 24, 2012
- International Business Machines Corporation
- Lurent Fournier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Verification of Address Translation Mechanisms
- Publication number 20090319961
- Publication date Dec 24, 2009
- International Buisiness Machines Corporation
- Yoav Avraham Katz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device, System and Method of Verification of Address Translation Me...
- Publication number 20080209160
- Publication date Aug 28, 2008
- Yoav Avraham Katz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling language and method for address translation design mechani...
- Publication number 20050278702
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Anatoly Koyfman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of mask-constrained floating-point addition and substrac...
- Publication number 20030200244
- Publication date Oct 23, 2003
- International Business Machines Corp.
- Ziv Abraham
- G06 - COMPUTING CALCULATING COUNTING

Anatoly Koyfman

Person

Patents Grantslast 30 patents

Diminution of test templates in test suites

Address translation stimuli generation for post-silicon functional...

Circuit modification

Mutations on input for test generation

Method and apparatus for post-silicon testing

Instruction-by-instruction checking on acceleration platforms

Verification of speculative execution

Method of verification of address translation mechanisms

Modeling language and method for address translation design mechani...

Generation of mask-constrained floating-point addition and subtract...

Patents Applicationslast 30 patents

DIMINUTION OF TEST TEMPLATES IN TEST SUITES

ADDRESS TRANSLATION STIMULI GENERATION FOR POST-SILICON FUNCTIONAL...

CIRCUIT MODIFICATION

Mutations on input for test generation

Partial Instruction-by-instruction checking on acceleration platforms

INSTRUCTION-BY-INSTRUCTION CHECKING ON ACCELERATION PLATFORMS

METHOD AND APPARATUS FOR POST-SILICON TESTING

VERIFICATION OF SPECULATIVE EXECUTION

Method of Verification of Address Translation Mechanisms

Device, System and Method of Verification of Address Translation Me...

Modeling language and method for address translation design mechani...

Generation of mask-constrained floating-point addition and substrac...