Andras Tantos

Person

Bellevue, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase lock loop (PLL) synchronization
- Patent number 12,191,865
- Issue date Jan 7, 2025
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip to chip time synchronization
- Patent number 12,184,752
- Issue date Dec 31, 2024
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase lock loop (PLL) synchronization
- Patent number 11,711,084
- Issue date Jul 25, 2023
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip to chip time synchronization
- Patent number 11,677,538
- Issue date Jun 13, 2023
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase lock loop (PLL) synchronization
- Patent number 11,329,653
- Issue date May 10, 2022
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip to chip time synchronization
- Patent number 11,153,067
- Issue date Oct 19, 2021
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase lock loop (PLL) synchronization
- Patent number 11,133,806
- Issue date Sep 28, 2021
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Direct memory access descriptor processing using timestamps
- Patent number 10,572,401
- Issue date Feb 25, 2020
- Microsoft Technology Licensing, LLC
- Chad McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access (“DMA”) descriptor processing using identifier...
- Patent number 10,528,494
- Issue date Jan 7, 2020
- Microsoft Technology Licensing, LLC
- Chad McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Display update time reduction for a near-eye display
- Patent number 10,514,541
- Issue date Dec 24, 2019
- Microsoft Technology Licensing, LLC
- Andras Tantos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Direct memory access descriptor processing
- Patent number 9,715,464
- Issue date Jul 25, 2017
- Microsoft Technology Licensing, LLC
- Chad McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding with integrated error-detection
- Patent number 9,455,745
- Issue date Sep 27, 2016
- Microsoft Technology Licensing, LLC
- Andras Tantos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Recalibration of a flexible mixed reality device
- Patent number 9,401,050
- Issue date Jul 26, 2016
- Microsoft Technology Licensing, LLC
- Elmer S. Cajigas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Recalibration of a flexible mixed reality device
- Patent number 9,311,883
- Issue date Apr 12, 2016
- Microsoft Technology Licensing, LLC
- Elmer S. Cajigas
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Invocation of accessory-specific user experience
- Patent number 8,719,112
- Issue date May 6, 2014
- Microsoft Corporation
- Todd L. Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic configuration of connectors for system-level communications
- Patent number 8,504,823
- Issue date Aug 6, 2013
- Microsoft Corporation
- Todd L. Carpenter
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Configurable connector for system-level communication
- Patent number 8,195,852
- Issue date Jun 5, 2012
- Microsoft Corporation
- Andras Tantos
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Configurable connector for system-level communication
- Patent number 7,865,629
- Issue date Jan 4, 2011
- Microsoft Corporation
- Andras Tantos
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
CHIP TO CHIP TIME SYNCHRONIZATION
- Publication number 20230403130
- Publication date Dec 14, 2023
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE LOCK LOOP (PLL) SYNCHRONIZATION
- Publication number 20230378960
- Publication date Nov 23, 2023
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE LOCK LOOP (PLL) SYNCHRONIZATION
- Publication number 20220231691
- Publication date Jul 21, 2022
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CHIP TO CHIP TIME SYNCHRONIZATION
- Publication number 20220006610
- Publication date Jan 6, 2022
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE LOCK LOOP (PLL) SYNCHRONIZATION
- Publication number 20210376837
- Publication date Dec 2, 2021
- Space Exploration Technologies Corp.
- David Francois Jacquet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CHIP TO CHIP TIME SYNCHRONIZATION
- Publication number 20200389287
- Publication date Dec 10, 2020
- Space Exploration Technologies Corp.
- Andras Tantos
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING
- Publication number 20170315939
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Chad MCBRIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING
- Publication number 20170315940
- Publication date Nov 2, 2017
- Microsoft Technology Licensing, LLC
- Chad MCBRIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING
- Publication number 20160283415
- Publication date Sep 29, 2016
- Chad McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECALIBRATION OF A FLEXIBLE MIXED REALITY DEVICE
- Publication number 20160117864
- Publication date Apr 28, 2016
- Microsoft Technology Licensing, LLC
- Elmer S. Cajigas
- G02 - OPTICS
Information Patent Application
ENCODING WITH INTEGRATED ERROR-DETECTION
- Publication number 20140237316
- Publication date Aug 21, 2014
- Andras Tantos
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INVOCATION OF ACCESSORY-SPECIFIC USER EXPERIENCE
- Publication number 20140229326
- Publication date Aug 14, 2014
- Microsoft Corporation
- Todd L. Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISPLAY UPDATE TIME REDUCTION FOR A NEAR-EYE DISPLAY
- Publication number 20140184475
- Publication date Jul 3, 2014
- Andras Tantos
- G02 - OPTICS
Information Patent Application
RECALIBRATION OF A FLEXIBLE MIXED REALITY DEVICE
- Publication number 20130120224
- Publication date May 16, 2013
- Elmer S. Cajigas
- G02 - OPTICS
Information Patent Application
CONFIGURABLE CONNECTOR FOR SYSTEM-LEVEL COMMUNICATION
- Publication number 20110125930
- Publication date May 26, 2011
- Microsoft Corporation
- Andras Tantos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF CONNECTORS FOR SYSTEM-LEVEL COMMUNICATIONS
- Publication number 20110126005
- Publication date May 26, 2011
- Microsoft Corporation
- Todd L. Carpenter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INVOCATION OF ACCESSORY-SPECIFIC USER EXPERIENCE
- Publication number 20110125601
- Publication date May 26, 2011
- Microsoft Corporation
- Todd L. Carpenter
- G06 - COMPUTING CALCULATING COUNTING

Andras Tantos

Person

Patents Grantslast 30 patents

Phase lock loop (PLL) synchronization

Chip to chip time synchronization

Phase lock loop (PLL) synchronization

Chip to chip time synchronization

Phase lock loop (PLL) synchronization

Chip to chip time synchronization

Phase lock loop (PLL) synchronization

Direct memory access descriptor processing using timestamps

Direct memory access (“DMA”) descriptor processing using identifier...

Display update time reduction for a near-eye display

Direct memory access descriptor processing

Encoding with integrated error-detection

Recalibration of a flexible mixed reality device

Recalibration of a flexible mixed reality device

Invocation of accessory-specific user experience

Dynamic configuration of connectors for system-level communications

Configurable connector for system-level communication

Configurable connector for system-level communication

Patents Applicationslast 30 patents

CHIP TO CHIP TIME SYNCHRONIZATION

PHASE LOCK LOOP (PLL) SYNCHRONIZATION

PHASE LOCK LOOP (PLL) SYNCHRONIZATION

CHIP TO CHIP TIME SYNCHRONIZATION

PHASE LOCK LOOP (PLL) SYNCHRONIZATION

CHIP TO CHIP TIME SYNCHRONIZATION

DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING

DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING

DIRECT MEMORY ACCESS DESCRIPTOR PROCESSING

RECALIBRATION OF A FLEXIBLE MIXED REALITY DEVICE

ENCODING WITH INTEGRATED ERROR-DETECTION

INVOCATION OF ACCESSORY-SPECIFIC USER EXPERIENCE

DISPLAY UPDATE TIME REDUCTION FOR A NEAR-EYE DISPLAY

RECALIBRATION OF A FLEXIBLE MIXED REALITY DEVICE

CONFIGURABLE CONNECTOR FOR SYSTEM-LEVEL COMMUNICATION

DYNAMIC CONFIGURATION OF CONNECTORS FOR SYSTEM-LEVEL COMMUNICATIONS

INVOCATION OF ACCESSORY-SPECIFIC USER EXPERIENCE