Andre P. Labonte

Person

Mechanicville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing optical device structures
- Patent number 12,158,605
- Issue date Dec 3, 2024
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Grant
Method for manufacturing optical device structures
- Patent number 12,013,566
- Issue date Jun 18, 2024
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Grant
Method for manufacturing optical device structures
- Patent number 11,487,058
- Issue date Nov 1, 2022
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Grant
Interconnect structures of semiconductor devices having a via struc...
- Patent number 11,380,581
- Issue date Jul 5, 2022
- GLOBALFOUNDRIES U.S. INC.
- Andre P. Labonte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming variable-depth device structures
- Patent number 11,112,694
- Issue date Sep 7, 2021
- Applied Materials, Inc.
- Andre P. LaBonte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 10,879,375
- Issue date Dec 29, 2020
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Insulating gate separation structure for transistor devices
- Patent number 10,879,073
- Issue date Dec 29, 2020
- GLOBALFOUNDRIES Inc.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure having reduced resistance variation and meth...
- Patent number 10,832,944
- Issue date Nov 10, 2020
- GLOBALFOUNDRIES Inc.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial gate spacer regions for gate contacts formed over the a...
- Patent number 10,832,961
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact structures
- Patent number 10,790,376
- Issue date Sep 29, 2020
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned buried contact for vertical field-effect transistor an...
- Patent number 10,770,585
- Issue date Sep 8, 2020
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate cut method after source/drain metallization
- Patent number 10,566,201
- Issue date Feb 18, 2020
- GLOBALFOUNDRIES Inc.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 10,522,654
- Issue date Dec 31, 2019
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contacting source and drain of a transistor device
- Patent number 10,468,300
- Issue date Nov 5, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local interconnect structure including non-eroded contact via trenches
- Patent number 10,388,602
- Issue date Aug 20, 2019
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 10,332,977
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Middle of the line (MOL) contacts with two-dimensional self-alignment
- Patent number 10,283,408
- Issue date May 7, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air-gap gate sidewall spacer and method
- Patent number 10,249,728
- Issue date Apr 2, 2019
- GLOBALFOUNDRIES Inc.
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact structure positioned above an active region of a trans...
- Patent number 10,243,053
- Issue date Mar 26, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming an air gap adjacent a gate of a transistor and a...
- Patent number 10,211,100
- Issue date Feb 19, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a semiconductor device with a gate contact posit...
- Patent number 10,204,994
- Issue date Feb 12, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 10,128,352
- Issue date Nov 13, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air-gap gate sidewall spacer and method
- Patent number 10,026,824
- Issue date Jul 17, 2018
- GLOBALFOUNDRIES Inc.
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for placing a gate contact inside a semiconduc...
- Patent number 10,014,215
- Issue date Jul 3, 2018
- GLOBALFOUNDRIES Inc.
- Andre Labonte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a gate contact for a transistor above an active...
- Patent number 9,947,589
- Issue date Apr 17, 2018
- GLOBALFOUNDRIES Inc.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for placing a gate contact inside an active re...
- Patent number 9,941,278
- Issue date Apr 10, 2018
- GLOBALFOUNDRIES Inc.
- Andre Labonte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 9,941,163
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 9,929,049
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Middle of the line (MOL) contacts with two-dimensional self-alignment
- Patent number 9,929,048
- Issue date Mar 27, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate tie-down enablement with inner spacer
- Patent number 9,899,259
- Issue date Feb 20, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES
- Publication number 20240295688
- Publication date Sep 5, 2024
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Application
UNIFORM SIGE CHANNEL IN NANOSHEET ARCHITECTURE
- Publication number 20240274724
- Publication date Aug 15, 2024
- Applied Materials, Inc.
- Jody A. Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES
- Publication number 20230021915
- Publication date Jan 26, 2023
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Application
METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES
- Publication number 20220050241
- Publication date Feb 17, 2022
- Applied Materials, Inc.
- Levent Colak
- G02 - OPTICS
Information Patent Application
METHODS OF FORMING VARIABLE-DEPTH DEVICE STRUCTURES
- Publication number 20200363719
- Publication date Nov 19, 2020
- Applied Materials, Inc.
- Andre P. LABONTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL GATE SPACER REGIONS FOR GATE CONTACTS FORMED OVER THE A...
- Publication number 20200335401
- Publication date Oct 22, 2020
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES
- Publication number 20200152512
- Publication date May 14, 2020
- GLOBALFOUNDRIES INC.
- Andre P. Labonte
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT STRUCTURE HAVING REDUCED RESISTANCE VARIATION AND METH...
- Publication number 20200144106
- Publication date May 7, 2020
- GLOBALFOUNDRIES INC.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES
- Publication number 20200135473
- Publication date Apr 30, 2020
- GLOBALFOUNDRIES INC.
- Chanro Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BURIED CONTACT FOR VERTICAL FIELD-EFFECT TRANSISTOR AN...
- Publication number 20200098913
- Publication date Mar 26, 2020
- GLOBALFOUNDRIES INC.
- Ruilong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT STRUCTURES
- Publication number 20200058757
- Publication date Feb 20, 2020
- GLOBALFOUNDRIES INC.
- Ruilong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20190363178
- Publication date Nov 28, 2019
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACTING SOURCE AND DRAIN OF A TRANSISTOR DEVICE
- Publication number 20190013241
- Publication date Jan 10, 2019
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20180374932
- Publication date Dec 27, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSIT...
- Publication number 20180286956
- Publication date Oct 4, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A...
- Publication number 20180277430
- Publication date Sep 27, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR-GAP GATE SIDEWALL SPACER AND METHOD
- Publication number 20180240883
- Publication date Aug 23, 2018
- GLOBALFOUNDRIES INC.
- DANIEL CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR-GAP GATE SIDEWALL SPACER AND METHOD
- Publication number 20180204927
- Publication date Jul 19, 2018
- GLOBALFOUNDRIES INC.
- DANIEL CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT
- Publication number 20180182668
- Publication date Jun 28, 2018
- GLOBALFOUNDRIES INC.
- RUILONG XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20180151433
- Publication date May 31, 2018
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUC...
- Publication number 20180012798
- Publication date Jan 11, 2018
- GLOBALFOUDRIES INC.
- Andre LABONTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE RE...
- Publication number 20180012887
- Publication date Jan 11, 2018
- GLOBALFOUNDRIES INC.
- Andre LABONTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170372959
- Publication date Dec 28, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170278753
- Publication date Sep 28, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170170070
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES
- Publication number 20170170118
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170162438
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH GATE CONTACT IN ACT...
- Publication number 20170092764
- Publication date Mar 30, 2017
- GLOBALFOUNDRIES INC.
- Ruilong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170047254
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
- Publication number 20170047252
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Su Chen Fan
- H01 - BASIC ELECTRIC ELEMENTS

Andre P. Labonte

Person

Patents Grantslast 30 patents

Method for manufacturing optical device structures

Method for manufacturing optical device structures

Method for manufacturing optical device structures

Interconnect structures of semiconductor devices having a via struc...

Methods of forming variable-depth device structures

Gate tie-down enablement with inner spacer

Insulating gate separation structure for transistor devices

Interconnect structure having reduced resistance variation and meth...

Sacrificial gate spacer regions for gate contacts formed over the a...

Contact structures

Self-aligned buried contact for vertical field-effect transistor an...

Gate cut method after source/drain metallization

Gate tie-down enablement with inner spacer

Contacting source and drain of a transistor device

Local interconnect structure including non-eroded contact via trenches

Gate tie-down enablement with inner spacer

Middle of the line (MOL) contacts with two-dimensional self-alignment

Air-gap gate sidewall spacer and method

Gate contact structure positioned above an active region of a trans...

Methods of forming an air gap adjacent a gate of a transistor and a...

Methods of forming a semiconductor device with a gate contact posit...

Gate tie-down enablement with inner spacer

Air-gap gate sidewall spacer and method

Method and apparatus for placing a gate contact inside a semiconduc...

Methods of forming a gate contact for a transistor above an active...

Method and apparatus for placing a gate contact inside an active re...

Gate tie-down enablement with inner spacer

Gate tie-down enablement with inner spacer

Middle of the line (MOL) contacts with two-dimensional self-alignment

Gate tie-down enablement with inner spacer

Patents Applicationslast 30 patents

METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES

UNIFORM SIGE CHANNEL IN NANOSHEET ARCHITECTURE

METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES

METHOD FOR MANUFACTURING OPTICAL DEVICE STRUCTURES

METHODS OF FORMING VARIABLE-DEPTH DEVICE STRUCTURES

SACRIFICIAL GATE SPACER REGIONS FOR GATE CONTACTS FORMED OVER THE A...

INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICES

INTERCONNECT STRUCTURE HAVING REDUCED RESISTANCE VARIATION AND METH...

INSULATING GATE SEPARATION STRUCTURE FOR TRANSISTOR DEVICES

SELF-ALIGNED BURIED CONTACT FOR VERTICAL FIELD-EFFECT TRANSISTOR AN...

CONTACT STRUCTURES

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

CONTACTING SOURCE AND DRAIN OF A TRANSISTOR DEVICE

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A GATE CONTACT POSIT...

METHODS OF FORMING AN AIR GAP ADJACENT A GATE OF A TRANSISTOR AND A...

AIR-GAP GATE SIDEWALL SPACER AND METHOD

AIR-GAP GATE SIDEWALL SPACER AND METHOD

MIDDLE OF THE LINE (MOL) CONTACTS WITH TWO-DIMENSIONAL SELF-ALIGNMENT

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE A SEMICONDUC...

METHOD AND APPARATUS FOR PLACING A GATE CONTACT INSIDE AN ACTIVE RE...

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

LOCAL INTERCONNECT STRUCTURE INCLUDING NON-ERODED CONTACT VIA TRENCHES

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

THREE-DIMENSIONAL SEMICONDUCTOR TRANSISTOR WITH GATE CONTACT IN ACT...

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER

GATE TIE-DOWN ENABLEMENT WITH INNER SPACER