Andre Schaefer

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 12,046,577
- Issue date Jul 23, 2024
- Tahoe Research, LTD.
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism for facilitating write tracking for following data eye mo...
- Patent number 10,853,216
- Issue date Dec 1, 2020
- Intel Corporation
- Tsun Ho Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management in multi-die assemblies
- Patent number 10,079,489
- Issue date Sep 18, 2018
- Intel Corporation
- Guido Droege
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated voltage regulators with magnetically enhanced inductors
- Patent number 9,921,640
- Issue date Mar 20, 2018
- Intel Corporation
- Uwe Zillmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-body-via isolated coaxial capacitor and techniques for form...
- Patent number 9,911,689
- Issue date Mar 6, 2018
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 9,768,148
- Issue date Sep 19, 2017
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for accessing a dynamic random access memory array
- Patent number 9,472,249
- Issue date Oct 18, 2016
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Power management in multi-die assemblies
- Patent number 9,391,453
- Issue date Jul 12, 2016
- Intel Corporation
- Guido Droege
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for power reduction in DRAM
- Patent number 9,361,970
- Issue date Jun 7, 2016
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically applying refresh overcharge voltage to extend refresh c...
- Patent number 9,311,983
- Issue date Apr 12, 2016
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Resonant clocking for three-dimensional stacked devices
- Patent number 9,287,196
- Issue date Mar 15, 2016
- Intel Corporation
- Ruchir Saraswat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlayer communications for 3D integrated circuit stack
- Patent number 9,263,422
- Issue date Feb 16, 2016
- Intel Corporation
- Guido Droege
- G11 - INFORMATION STORAGE
Information Patent Grant
Separate microchannel voltage domains in stacked memory architecture
- Patent number 9,230,614
- Issue date Jan 5, 2016
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully integrated voltage regulators for multi-stack integrated circ...
- Patent number 9,229,466
- Issue date Jan 5, 2016
- Intel Corporation
- Ruchir Saraswat
- G05 - CONTROLLING REGULATING
Information Patent Grant
Techniques for accessing a dynamic random access memory array
- Patent number 9,135,982
- Issue date Sep 15, 2015
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism for facilitating write tracking for following data eye mo...
- Patent number 9,086,881
- Issue date Jul 21, 2015
- Intel Corporation
- Tsun Ho Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sense amplifier voltage modulation
- Patent number 9,087,559
- Issue date Jul 21, 2015
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive address mapping with dynamic runtime memory mapping selection
- Patent number 9,026,767
- Issue date May 5, 2015
- Intel Corporation
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interlayer communications for 3D integrated circuit stack
- Patent number 9,000,577
- Issue date Apr 7, 2015
- Intel Corporation
- Guido Droege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 8,971,087
- Issue date Mar 3, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for accessing memory
- Patent number 8,959,271
- Issue date Feb 17, 2015
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for power reduction in DRAM
- Patent number 8,811,110
- Issue date Aug 19, 2014
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Energy efficient power distribution for 3D integrated circuit stack
- Patent number 8,547,769
- Issue date Oct 1, 2013
- Intel Corporation
- Ruchir Saraswat
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive address mapping with dynamic runtime memory mapping selection
- Patent number 8,135,936
- Issue date Mar 13, 2012
- Intel Corporation
- Andre Schaefer
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fast data eye retraining for a memory
- Patent number 8,037,375
- Issue date Oct 11, 2011
- Intel Corporation
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of transferring signals between a memory device and a memory...
- Patent number 7,587,655
- Issue date Sep 8, 2009
- Infineon Technologies AG
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Grant
Device in a memory circuit for definition of waiting times
- Patent number 7,355,921
- Issue date Apr 8, 2008
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Driver circuit for binary signals
- Patent number 7,321,240
- Issue date Jan 22, 2008
- Infineon Technologies AG
- Andre Schaefer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differental current source for generating DRAM refresh signal
- Patent number 7,180,805
- Issue date Feb 20, 2007
- Infineon Technologies AG
- Joachim Schnabel
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit device with clock pulse detection facility
- Patent number 7,068,079
- Issue date Jun 27, 2006
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20240379625
- Publication date Nov 14, 2024
- Tahoe Research, Ltd.
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20190304953
- Publication date Oct 3, 2019
- Intel Corporation
- Pete D. VOGT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
- Publication number 20180122779
- Publication date May 3, 2018
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
THROUGH-BODY-VIA ISOLATED COAXIAL CAPACITOR AND TECHNIQUES FOR FORM...
- Publication number 20170040255
- Publication date Feb 9, 2017
- Intel Corporation
- KEVIN J. LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES
- Publication number 20170011779
- Publication date Jan 12, 2017
- Intel Corporation
- Guido Droege
- G11 - INFORMATION STORAGE
Information Patent Application
DATA REORDER DURING MEMORY ACCESS
- Publication number 20160306566
- Publication date Oct 20, 2016
- Shih-Lien L. Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY APPLYING REFRESH OVERCHARGE VOLTAGE TO EXTEND REFRESH C...
- Publication number 20150380072
- Publication date Dec 31, 2015
- ANDRE SCHAEFER
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for Accessing a Dynamic Random Access Memory Array
- Publication number 20150357011
- Publication date Dec 10, 2015
- Intel Corporation
- ANDRE SCHAEFER
- G11 - INFORMATION STORAGE
Information Patent Application
MECHANISM FOR FACILITATING WRITE TRACKING FOR FOLLOWING DATA EYE MO...
- Publication number 20150317228
- Publication date Nov 5, 2015
- Intel Corporation
- Tsun Ho LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Accessing a Dynamic Random Access Memory Array
- Publication number 20150170729
- Publication date Jun 18, 2015
- ANDRE SCHAEFER
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK
- Publication number 20150130534
- Publication date May 14, 2015
- Intel Corporation
- Guido Droege
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20150108660
- Publication date Apr 23, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES
- Publication number 20150003181
- Publication date Jan 1, 2015
- Guido Droege
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION FOR POWER REDUCTION IN DRAM
- Publication number 20140325136
- Publication date Oct 30, 2014
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ACCESSING MEMORY
- Publication number 20140281193
- Publication date Sep 18, 2014
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SENSE AMPLIFIER VOLTAGE MODULATION
- Publication number 20140185392
- Publication date Jul 3, 2014
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES
- Publication number 20140183691
- Publication date Jul 3, 2014
- Ruchir Saraswat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS
- Publication number 20140092574
- Publication date Apr 3, 2014
- Uwe ZILLMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION FOR POWER REDUCTION IN DRAM
- Publication number 20140006700
- Publication date Jan 2, 2014
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR FACILITATING WRITE TRACKING FOR FOLLOWING DATA EYE MO...
- Publication number 20140006702
- Publication date Jan 2, 2014
- Tsun Ho Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY INTEGRATED VOLTAGE REGULATORS FOR MULTI-STACK INTEGRATED CIRC...
- Publication number 20130335059
- Publication date Dec 19, 2013
- Intel Corporation
- Ruchir Saraswat
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK
- Publication number 20130293292
- Publication date Nov 7, 2013
- Guido Droege
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE
- Publication number 20130279276
- Publication date Oct 24, 2013
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20130272049
- Publication date Oct 17, 2013
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection
- Publication number 20130246734
- Publication date Sep 19, 2013
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack
- Publication number 20120250443
- Publication date Oct 4, 2012
- RUCHIR SARASWAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION
- Publication number 20110153908
- Publication date Jun 23, 2011
- Intel Corporation
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast data eye retraining for a memory
- Publication number 20100332921
- Publication date Dec 30, 2010
- Andre Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of transferring signals between a memory device and a memory...
- Publication number 20070091711
- Publication date Apr 26, 2007
- Paul Wallner
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory system, semiconductor memory chip, and method...
- Publication number 20070061494
- Publication date Mar 15, 2007
- Paul Wallner
- G11 - INFORMATION STORAGE

Andre Schaefer

Person

Patents Grantslast 30 patents

Stacked memory with interface providing offset interconnects

Mechanism for facilitating write tracking for following data eye mo...

Power management in multi-die assemblies

Integrated voltage regulators with magnetically enhanced inductors

Through-body-via isolated coaxial capacitor and techniques for form...

Stacked memory with interface providing offset interconnects

Techniques for accessing a dynamic random access memory array

Power management in multi-die assemblies

Configuration for power reduction in DRAM

Dynamically applying refresh overcharge voltage to extend refresh c...

Resonant clocking for three-dimensional stacked devices

Interlayer communications for 3D integrated circuit stack

Separate microchannel voltage domains in stacked memory architecture

Fully integrated voltage regulators for multi-stack integrated circ...

Techniques for accessing a dynamic random access memory array

Mechanism for facilitating write tracking for following data eye mo...

Memory sense amplifier voltage modulation

Adaptive address mapping with dynamic runtime memory mapping selection

Interlayer communications for 3D integrated circuit stack

Stacked memory with interface providing offset interconnects

System and method for accessing memory

Configuration for power reduction in DRAM

Energy efficient power distribution for 3D integrated circuit stack

Adaptive address mapping with dynamic runtime memory mapping selection

Fast data eye retraining for a memory

Method of transferring signals between a memory device and a memory...

Device in a memory circuit for definition of waiting times

Driver circuit for binary signals

Differental current source for generating DRAM refresh signal

Circuit device with clock pulse detection facility

Patents Applicationslast 30 patents

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

THROUGH-BODY-VIA ISOLATED COAXIAL CAPACITOR AND TECHNIQUES FOR FORM...

POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES

DATA REORDER DURING MEMORY ACCESS

DYNAMICALLY APPLYING REFRESH OVERCHARGE VOLTAGE TO EXTEND REFRESH C...

Techniques for Accessing a Dynamic Random Access Memory Array

MECHANISM FOR FACILITATING WRITE TRACKING FOR FOLLOWING DATA EYE MO...

Techniques for Accessing a Dynamic Random Access Memory Array

INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

POWER MANAGEMENT IN MULTI-DIE ASSEMBLIES

CONFIGURATION FOR POWER REDUCTION IN DRAM

SYSTEM AND METHOD FOR ACCESSING MEMORY

MEMORY SENSE AMPLIFIER VOLTAGE MODULATION

RESONANT CLOCKING FOR THREE-DIMENSIONAL STACKED DEVICES

INTEGRATED VOLTAGE REGULATORS WITH MAGNETICALLY ENHANCED INDUCTORS

CONFIGURATION FOR POWER REDUCTION IN DRAM

MECHANISM FOR FACILITATING WRITE TRACKING FOR FOLLOWING DATA EYE MO...

FULLY INTEGRATED VOLTAGE REGULATORS FOR MULTI-STACK INTEGRATED CIRC...

INTERLAYER COMMUNICATIONS FOR 3D INTEGRATED CIRCUIT STACK

SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION

Fast data eye retraining for a memory

Method of transferring signals between a memory device and a memory...

Semiconductor memory system, semiconductor memory chip, and method...