Andre Steimle

Person

Evry, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Self-synchronizing bit error analyzer and circuit
- Patent number 7,661,039
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Gerard Boudon
- G01 - MEASURING TESTING
Information Patent Grant
Self-synchronising bit error analyser and circuit
- Patent number 7,404,115
- Issue date Jul 22, 2008
- International Business Machines Corporation
- Gerard Boudon
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit for performing the integrity diagnostic of an ar...
- Patent number 6,535,862
- Issue date Mar 18, 2003
- International Business Machines Corporation
- Didier Louis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural chip architecture and neural networks incorporated therein
- Patent number 6,523,018
- Issue date Feb 18, 2003
- International Business Machines Corporation
- Didier Louis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuron architecture having a dual structure and neural networks inc...
- Patent number 6,502,083
- Issue date Dec 31, 2002
- International Business Machines Corporation
- Didier Louis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing automatic learning according to the K nearest neighbor...
- Patent number 6,377,941
- Issue date Apr 23, 2002
- International Business Machines Corporation
- Andre Steimle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural semiconductor chip and neural networks incorporated therein
- Patent number 5,717,832
- Issue date Feb 10, 1998
- International Business Machines Corporation
- Andre Steimle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Daisy chain circuit for serial connection of neuron circuits
- Patent number 5,710,869
- Issue date Jan 20, 1998
- International Business Machines Corporation
- Catherine Godefroy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for pre-charging a free neuron circuit
- Patent number 5,701,397
- Issue date Dec 23, 1997
- International Business Machines Corporation
- Andre Steimle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuron circuit
- Patent number 5,621,863
- Issue date Apr 15, 1997
- International Business Machines Corporation
- Jean-Yves Boulet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for argument reduction in exponential computations of IEE...
- Patent number 5,463,574
- Issue date Oct 31, 1995
- International Business Machines Corporation
- Bernard Desrosiers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for optimizing argument reduction
- Patent number 5,452,241
- Issue date Sep 19, 1995
- International Business Machines Corporation
- Bernard Desrosiers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for executing add/sub operations between IEEE standard fl...
- Patent number 5,337,265
- Issue date Aug 9, 1994
- International Business Machines Corporation
- Bernard Desrosiers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Self-synchronizing bit error analyzer and circuit
- Publication number 20090019326
- Publication date Jan 15, 2009
- Gerard Boudon
- G01 - MEASURING TESTING
Information Patent Application
SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT
- Publication number 20070011534
- Publication date Jan 11, 2007
- International Business Machines Corporation
- Gerard Boudon
- G01 - MEASURING TESTING

Andre Steimle

Person

Patents Grantslast 30 patents

Self-synchronizing bit error analyzer and circuit

Self-synchronising bit error analyser and circuit

Method and circuit for performing the integrity diagnostic of an ar...

Neural chip architecture and neural networks incorporated therein

Neuron architecture having a dual structure and neural networks inc...

Implementing automatic learning according to the K nearest neighbor...

Neural semiconductor chip and neural networks incorporated therein

Daisy chain circuit for serial connection of neuron circuits

Circuit for pre-charging a free neuron circuit

Neuron circuit

Apparatus for argument reduction in exponential computations of IEE...

System for optimizing argument reduction

Apparatus for executing add/sub operations between IEEE standard fl...

Patents Applicationslast 30 patents

Self-synchronizing bit error analyzer and circuit

SELF-SYNCHRONISING BIT ERROR ANALYSER AND CIRCUIT