Andreas Moser

Person

Maria Rain, AT

People

Patents Grantslast 30 patents

Information Patent Grant
Method for processing a semiconductor wafer, semiconductor composit...
- Patent number 11,515,264
- Issue date Nov 29, 2022
- Infineon Technologies AG
- Francisco Javier Santos Rodriguez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation structure for IGBT devices having an integrated diode
- Patent number 11,075,291
- Issue date Jul 27, 2021
- Infineon Technologies Austria AG
- Matteo Dainese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device with epitaxial layer...
- Patent number 10,923,432
- Issue date Feb 16, 2021
- Infineon Technologies Austria AG
- Andreas Moser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device
- Patent number 10,825,716
- Issue date Nov 3, 2020
- Infineon Technologies AG
- Andreas Moser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage termination structure of a power semiconductor device
- Patent number 10,600,862
- Issue date Mar 24, 2020
- Infineon Technologies Austria AG
- Erich Griebl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device with epitaxial layer...
- Patent number 10,600,740
- Issue date Mar 24, 2020
- Infineon Technologies Austria AG
- Andreas Moser
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Buried insulator regions and methods of formation thereof
- Patent number 10,410,911
- Issue date Sep 10, 2019
- Infineon Technologies AG
- Carsten Schaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor device with epitaxial layer...
- Patent number 10,236,258
- Issue date Mar 19, 2019
- Infineon Technologies Austria AG
- Andreas Moser
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of manufacturing a semiconductor device with epitaxial layer...
- Patent number 9,711,357
- Issue date Jul 18, 2017
- Infineon Technologies Austria AG
- Hans Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for processing a substrate and a method of process screening...
- Patent number 9,406,572
- Issue date Aug 2, 2016
- Infineon Technologies AG
- Rudolf Zelsacher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Edge termination structure with trench isolation regions
- Patent number 9,224,806
- Issue date Dec 29, 2015
- Infineon Technologies AG
- Stephan Voss
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Processing a Semiconductor Wafer and Semiconductor Compo...
- Publication number 20220359428
- Publication date Nov 10, 2022
- Francisco Javier Santos Rodriguez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Manufacturing a Semiconductor Device with Epitaxial Layer...
- Publication number 20200185335
- Publication date Jun 11, 2020
- Andreas Moser
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for Processing a Semiconductor Wafer, Semiconductor Composit...
- Publication number 20190363057
- Publication date Nov 28, 2019
- Francisco Javier Santos Rodriguez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Manufacturing a Semiconductor Device with Epitaxial Layer...
- Publication number 20190181094
- Publication date Jun 13, 2019
- Andreas Moser
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for Manufacturing a Semiconductor Device
- Publication number 20190148217
- Publication date May 16, 2019
- Andreas Moser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Insulator Regions and Methods of Formation Thereof
- Publication number 20180166324
- Publication date Jun 14, 2018
- INFINEON TECHNOLOGIES AG
- Carsten Schaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Voltage Termination Structure of a Power Semiconductor Device
- Publication number 20180114830
- Publication date Apr 26, 2018
- Infineon Technologies Austria AG
- Erich Griebl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Manufacturing a Semiconductor Device with Epitaxial Layer...
- Publication number 20170186695
- Publication date Jun 29, 2017
- Infineon Technologies Austria AG
- Andreas Moser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PROCESSING A SUBSTRATE AND A METHOD OF PROCESS SCREENING...
- Publication number 20160126149
- Publication date May 5, 2016
- INFINEON TECHNOLOGIES AG
- Rudolf Zelsacher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Edge Termination Structure with Trench Isolation Regions
- Publication number 20150041946
- Publication date Feb 12, 2015
- INFINEON TECHNOLOGIES AG
- Stephan Voss
- H01 - BASIC ELECTRIC ELEMENTS

Andreas Moser

Person

Patents Grantslast 30 patents

Method for processing a semiconductor wafer, semiconductor composit...

Isolation structure for IGBT devices having an integrated diode

Method of manufacturing a semiconductor device with epitaxial layer...

Method for manufacturing a semiconductor device

High voltage termination structure of a power semiconductor device

Method of manufacturing a semiconductor device with epitaxial layer...

Buried insulator regions and methods of formation thereof

Method of manufacturing a semiconductor device with epitaxial layer...

Method of manufacturing a semiconductor device with epitaxial layer...

Method for processing a substrate and a method of process screening...

Edge termination structure with trench isolation regions

Patents Applicationslast 30 patents

Method for Processing a Semiconductor Wafer and Semiconductor Compo...

Method of Manufacturing a Semiconductor Device with Epitaxial Layer...

Method for Processing a Semiconductor Wafer, Semiconductor Composit...

Method of Manufacturing a Semiconductor Device with Epitaxial Layer...

Method for Manufacturing a Semiconductor Device

Buried Insulator Regions and Methods of Formation Thereof

High Voltage Termination Structure of a Power Semiconductor Device

Method of Manufacturing a Semiconductor Device with Epitaxial Layer...

METHOD FOR PROCESSING A SUBSTRATE AND A METHOD OF PROCESS SCREENING...

Edge Termination Structure with Trench Isolation Regions