Andres Rafael Takach

Person

Wilsonville, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Formal verification using microtransactions
- Patent number 10,515,168
- Issue date Dec 24, 2019
- Mentor Graphics Corporation
- Pankaj P. Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification using microtransactions
- Patent number 9,817,929
- Issue date Nov 14, 2017
- Calypto Design Systems, Inc.
- Pankaj P. Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonsequential hardware design synthesis verification
- Patent number 8,219,949
- Issue date Jul 10, 2012
- Calypto Design Systems, Inc.
- Robert J. Condon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured algorithmic programming language approach to system design
- Patent number 8,205,175
- Issue date Jun 19, 2012
- Calypto Design Systems, Inc.
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loop manipulation if a behavioral synthesis tool
- Patent number 7,840,931
- Issue date Nov 23, 2010
- Mentor Graphics Corporation
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loop manipulation in a behavioral synthesis tool
- Patent number 7,412,684
- Issue date Aug 12, 2008
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of memory accesses in a circuit design
- Patent number 7,353,491
- Issue date Apr 1, 2008
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured algorithmic programming language approach to system design
- Patent number 7,308,672
- Issue date Dec 11, 2007
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured algorithmic programming language approach to system design
- Patent number 6,701,501
- Issue date Mar 2, 2004
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Nonsequential Hardware Design Synthesis Verification
- Publication number 20110055779
- Publication date Mar 3, 2011
- Robert Condon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layered Modeling for High-Level Synthesis of Electronic Designs
- Publication number 20110035204
- Publication date Feb 10, 2011
- Maxim Smirnov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF MEMORY ACCESSES IN A CIRCUIT DESIGN
- Publication number 20080148215
- Publication date Jun 19, 2008
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED ALGORITHMIC PROGRAMMING LANGUAGE APPROACH TO SYSTEM DESIGN
- Publication number 20080141227
- Publication date Jun 12, 2008
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of memory accesses in a circuit design
- Publication number 20050273752
- Publication date Dec 8, 2005
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Loop manipulation in a behavioral synthesis tool
- Publication number 20050268271
- Publication date Dec 1, 2005
- Mentor Graphics Corporation
- Peter Pius Gutberlet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structured algorithmic programming language approach to system design
- Publication number 20040143801
- Publication date Jul 22, 2004
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structured algorithmic programming language approach to system design
- Publication number 20020133788
- Publication date Sep 19, 2002
- Simon Joshua Waters
- G06 - COMPUTING CALCULATING COUNTING

Andres Rafael Takach

Person

Patents Grantslast 30 patents

Formal verification using microtransactions

Formal verification using microtransactions

Nonsequential hardware design synthesis verification

Structured algorithmic programming language approach to system design

Loop manipulation if a behavioral synthesis tool

Loop manipulation in a behavioral synthesis tool

Optimization of memory accesses in a circuit design

Structured algorithmic programming language approach to system design

Structured algorithmic programming language approach to system design

Patents Applicationslast 30 patents

Nonsequential Hardware Design Synthesis Verification

Layered Modeling for High-Level Synthesis of Electronic Designs

OPTIMIZATION OF MEMORY ACCESSES IN A CIRCUIT DESIGN

STRUCTURED ALGORITHMIC PROGRAMMING LANGUAGE APPROACH TO SYSTEM DESIGN

Optimization of memory accesses in a circuit design

Loop manipulation in a behavioral synthesis tool

Structured algorithmic programming language approach to system design

Structured algorithmic programming language approach to system design