Andrew A. Turner

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic guard band with timing protection and with performance prot...
- Patent number 11,989,071
- Issue date May 21, 2024
- International Business Machines Corporation
- Tobias Webel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic guard band with timing protection and with performance prot...
- Patent number 11,953,982
- Issue date Apr 9, 2024
- International Business Machines Corporation
- Alejandro Alberto Cook Lobo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Portable chip tester with integrated field programmable gate array
- Patent number 11,226,372
- Issue date Jan 18, 2022
- International Business Machines Corporation
- Noah Singer
- G01 - MEASURING TESTING
Information Patent Grant
Tunable power save loop for processor chips
- Patent number 11,169,841
- Issue date Nov 9, 2021
- Internationl Business Machines Corporation
- K Paul Muller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance-screen ring oscillator with switchable features
- Patent number 11,146,251
- Issue date Oct 12, 2021
- International Business Machines Corporation
- John B. DeForge
- G01 - MEASURING TESTING
Information Patent Grant
Testing mechanism for a proximity fail probability of defects acros...
- Patent number 10,768,226
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Kirk D. Peterson
- G01 - MEASURING TESTING
Information Patent Grant
Functional logic cone signature generation for circuit analysis
- Patent number 10,726,178
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Nicholai L'Esperance
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor power and performance optimization
- Patent number 10,215,804
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Sean M. Carey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing mechanism for a proximity fail probability of defects acros...
- Patent number 10,114,071
- Issue date Oct 30, 2018
- International Business Machines Corporation
- Kirk D. Peterson
- G01 - MEASURING TESTING
Information Patent Grant
Method for enhanced semiconductor product diagnostic fail signature...
- Patent number 10,101,388
- Issue date Oct 16, 2018
- International Business Machines Corporation
- Robert C. Redburn
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for offline supported adaptive testing
- Patent number 9,921,264
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Andrew A. Turner
- G01 - MEASURING TESTING
Information Patent Grant
Optimized chain diagnostic fail isolation
- Patent number 9,733,307
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Gerard M. Salem
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic noise mitigation in integrated circuit devices using local...
- Patent number 9,712,112
- Issue date Jul 18, 2017
- International Business Machines Corporation
- Miles C. Pedrone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimizing generation of test configurations for built-in self-testing
- Patent number 9,588,177
- Issue date Mar 7, 2017
- International Business Machines Corporation
- Eugene R. Atwood
- G01 - MEASURING TESTING
Information Patent Grant
Methodology of grading reliability and performance of chips across...
- Patent number 9,575,115
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Nathaniel R. Chadwick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Physically aware insertion of diagnostic circuit elements
- Patent number 9,557,381
- Issue date Jan 31, 2017
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Method of self-correcting power grid for semiconductor structures
- Patent number 9,214,427
- Issue date Dec 15, 2015
- GLOBALFOUNDRIES Inc.
- Cathryn J. Christiansen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-correcting power grid for semiconductor structures method
- Patent number 9,087,841
- Issue date Jul 21, 2015
- International Business Machines Corporation
- Cathryn J. Christiansen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Updating interface settings for an interface
- Patent number 9,008,196
- Issue date Apr 14, 2015
- International Business Machines Corporation
- Frank W. Angelotti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating deep trenches on underlying substrate
- Patent number 8,860,113
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Creating deep trenches on underlying substrate
- Patent number 8,586,444
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC GUARD BAND WITH TIMING PROTECTION AND WITH PERFORMANCE PROT...
- Publication number 20240028447
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Alejandro Alberto Cook Lobo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC GUARD BAND WITH TIMING PROTECTION AND WITH PERFORMANCE PROT...
- Publication number 20240028095
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Tobias Webel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TUNABLE POWER SAVE LOOP FOR PROCESSOR CHIPS
- Publication number 20210294640
- Publication date Sep 23, 2021
- International Business Machines Corporation
- K Paul Muller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE-SCREEN RING OSCILLATOR WITH SWITCHABLE FEATURES
- Publication number 20210281248
- Publication date Sep 9, 2021
- International Business Machines Corporation
- John B. DeForge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PORTABLE CHIP TESTER WITH INTEGRATED FIELD PROGRAMMABLE GATE ARRAY
- Publication number 20210109154
- Publication date Apr 15, 2021
- International Business Machines Corporation
- Noah Singer
- G01 - MEASURING TESTING
Information Patent Application
TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROS...
- Publication number 20180372799
- Publication date Dec 27, 2018
- International Business Machines Corporation
- KIRK D. PETERSON
- G01 - MEASURING TESTING
Information Patent Application
Method and Apparatus for Offline Supported Adaptive Testing
- Publication number 20180136273
- Publication date May 17, 2018
- International Business Machines Corporation
- Andrew A. TURNER
- G01 - MEASURING TESTING
Information Patent Application
SEMICONDUCTOR POWER AND PERFORMANCE OPTIMIZATION
- Publication number 20180031630
- Publication date Feb 1, 2018
- International Business Machines Corporation
- Sean M. Carey
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR OFFLINE SUPPORTED ADAPTIVE TESTING
- Publication number 20170307679
- Publication date Oct 26, 2017
- International Business Machines Corporation
- Andrew A. TURNER
- G01 - MEASURING TESTING
Information Patent Application
TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROS...
- Publication number 20170307685
- Publication date Oct 26, 2017
- International Business Machines Corporation
- KIRK D. PETERSON
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR ENHANCED SEMICONDUCTOR PRODUCT DIAGNOSTIC FAIL SIGNATURE...
- Publication number 20170168112
- Publication date Jun 15, 2017
- International Business Machines Corporation
- Robert C. Redburn
- G01 - MEASURING TESTING
Information Patent Application
METHOD OFSELF-CORRECTING A POWER GRID FOR SEMICONDUCTOR STRUCTURES
- Publication number 20150243601
- Publication date Aug 27, 2015
- International Business Machines Corporation
- Cathryn J. Christiansen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES METHOD
- Publication number 20150115400
- Publication date Apr 30, 2015
- International Business Machines Corporation
- Cathryn J. Christiansen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS...
- Publication number 20140107822
- Publication date Apr 17, 2014
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G01 - MEASURING TESTING
Information Patent Application
CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
- Publication number 20140021585
- Publication date Jan 23, 2014
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE
- Publication number 20130249052
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Jennifer E. Appleyard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UPDATING INTERFACE SETTINGS FOR AN INTERFACE
- Publication number 20120278519
- Publication date Nov 1, 2012
- International Business Machines Corporation
- Frank W. Angelotti
- G06 - COMPUTING CALCULATING COUNTING

Andrew A. Turner

Person

Patents Grantslast 30 patents

Dynamic guard band with timing protection and with performance prot...

Dynamic guard band with timing protection and with performance prot...

Portable chip tester with integrated field programmable gate array

Tunable power save loop for processor chips

Performance-screen ring oscillator with switchable features

Testing mechanism for a proximity fail probability of defects acros...

Functional logic cone signature generation for circuit analysis

Semiconductor power and performance optimization

Testing mechanism for a proximity fail probability of defects acros...

Method for enhanced semiconductor product diagnostic fail signature...

Method and apparatus for offline supported adaptive testing

Optimized chain diagnostic fail isolation

Dynamic noise mitigation in integrated circuit devices using local...

Optimizing generation of test configurations for built-in self-testing

Methodology of grading reliability and performance of chips across...

Physically aware insertion of diagnostic circuit elements

Method of self-correcting power grid for semiconductor structures

Self-correcting power grid for semiconductor structures method

Updating interface settings for an interface

Creating deep trenches on underlying substrate

Creating deep trenches on underlying substrate

Patents Applicationslast 30 patents

DYNAMIC GUARD BAND WITH TIMING PROTECTION AND WITH PERFORMANCE PROT...

DYNAMIC GUARD BAND WITH TIMING PROTECTION AND WITH PERFORMANCE PROT...

TUNABLE POWER SAVE LOOP FOR PROCESSOR CHIPS

PERFORMANCE-SCREEN RING OSCILLATOR WITH SWITCHABLE FEATURES

PORTABLE CHIP TESTER WITH INTEGRATED FIELD PROGRAMMABLE GATE ARRAY

TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROS...

Method and Apparatus for Offline Supported Adaptive Testing

SEMICONDUCTOR POWER AND PERFORMANCE OPTIMIZATION

METHOD AND APPARATUS FOR OFFLINE SUPPORTED ADAPTIVE TESTING

TESTING MECHANISM FOR A PROXIMITY FAIL PROBABILITY OF DEFECTS ACROS...

METHOD FOR ENHANCED SEMICONDUCTOR PRODUCT DIAGNOSTIC FAIL SIGNATURE...

METHOD OFSELF-CORRECTING A POWER GRID FOR SEMICONDUCTOR STRUCTURES

SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES METHOD

METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS...

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE

CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE

UPDATING INTERFACE SETTINGS FOR AN INTERFACE