Andrew B. Kahng

Person

Del Mar, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-die IC layout methods with awareness of mix and match die int...
- Patent number 10,713,406
- Issue date Jul 14, 2020
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC layout adjustment method and tool for improving dielectric relia...
- Patent number 9,922,161
- Issue date Mar 20, 2018
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accuracy configurable adders and methods
- Patent number 9,229,686
- Issue date Jan 5, 2016
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-length biasing for digital circuit optimization
- Patent number 9,202,003
- Issue date Dec 1, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 9,069,926
- Issue date Jun 30, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,949,768
- Issue date Feb 3, 2015
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,869,094
- Issue date Oct 21, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,756,555
- Issue date Jun 17, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout decomposition for double patterning lithography
- Patent number 8,751,974
- Issue date Jun 10, 2014
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,635,583
- Issue date Jan 21, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells having transistors annotated for gate-length biasing
- Patent number 8,490,043
- Issue date Jul 16, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout decomposition for double patterning lithography
- Patent number 8,402,396
- Issue date Mar 19, 2013
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for gate-length biasing using annotation data
- Patent number 8,185,865
- Issue date May 22, 2012
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-length biasing for digital circuit optimization
- Patent number 8,127,266
- Issue date Feb 28, 2012
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tool for modifying mask design layout
- Patent number 8,103,981
- Issue date Jan 24, 2012
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Internet telephony through hosts
- Patent number 8,073,977
- Issue date Dec 6, 2011
- The Regents of the University of California
- Jonathan Cox
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for wafer topography-aware integrated circuit des...
- Patent number 8,024,675
- Issue date Sep 20, 2011
- Tela Innovations, Inc.
- Puneet Gupta
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for detecting lithographic hotspots in a circu...
- Patent number 7,945,870
- Issue date May 17, 2011
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for designing an integrated circuit in...
- Patent number 7,873,929
- Issue date Jan 18, 2011
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for performing transistor-level static performanc...
- Patent number 7,865,856
- Issue date Jan 4, 2011
- Tela Innovations, Inc.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of designing a digital circuit by correlating different stat...
- Patent number 7,823,098
- Issue date Oct 26, 2010
- Tela Innovations, Inc.
- Cho W. Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for topography-aware reticle enhancement
- Patent number 7,814,456
- Issue date Oct 12, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Arrangement of fill unit elements in an integrated circuit intercon...
- Patent number 7,745,239
- Issue date Jun 29, 2010
- Tela Innovations, Inc.
- O. Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for finding an equivalent circuit representation...
- Patent number 7,743,349
- Issue date Jun 22, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reshaping a transistor gate in an integrated...
- Patent number 7,730,432
- Issue date Jun 1, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for integrated circuit optimization by using an o...
- Patent number 7,716,612
- Issue date May 11, 2010
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout description having enhanced fill annotation
- Patent number 7,676,772
- Issue date Mar 9, 2010
- Tela Innovations, Inc.
- O. Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for placing layout objects in a standard-cell layout
- Patent number 7,640,522
- Issue date Dec 29, 2009
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for varying the starting conditions for a resolut...
- Patent number 7,627,849
- Issue date Dec 1, 2009
- Tela Innovations, Inc.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for correcting a mask design layout
- Patent number 7,614,032
- Issue date Nov 3, 2009
- The Regents of the Univerisity of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED-CIRCUIT GLOBAL ROUTING METHOD
- Publication number 20230205968
- Publication date Jun 29, 2023
- The Regents of the University of California
- Andrew Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE IC LAYOUT METHODS WITH AWARENESS OF MIX AND MATCH DIE INT...
- Publication number 20180341738
- Publication date Nov 29, 2018
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IC LAYOUT ADJUSTMENT METHOD AND TOOL FOR IMPROVING DIELECTRIC RELIA...
- Publication number 20150379188
- Publication date Dec 31, 2015
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20140245245
- Publication date Aug 28, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gate-Length Biasing for Digital Circuit Optimization
- Publication number 20140223404
- Publication date Aug 7, 2014
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCURACY CONFIGURABLE ADDERS AND METHODS
- Publication number 20140059105
- Publication date Feb 27, 2014
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cells having transistors annotated for gate-length biasing
- Publication number 20130254734
- Publication date Sep 26, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY
- Publication number 20130159945
- Publication date Jun 20, 2013
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014072
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014073
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20130014071
- Publication date Jan 10, 2013
- Tela Innovations, Inc.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY
- Publication number 20110078638
- Publication date Mar 31, 2011
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA
- Publication number 20100169846
- Publication date Jul 1, 2010
- Tela Innovations. Inc., a Delaware Corporation
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING
- Publication number 20100169847
- Publication date Jul 1, 2010
- Tela Innovations. Inc., a Delaware Corporation
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOOL FOR MODIFYING MASK DESIGN LAYOUT
- Publication number 20100023917
- Publication date Jan 28, 2010
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for detecting lithographic hotspots
- Publication number 20080235645
- Publication date Sep 25, 2008
- The Regents of the University of California.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Auxiliary pattern generation for cell-based optical proximity corre...
- Publication number 20080066041
- Publication date Mar 13, 2008
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for correcting a mask design layout
- Publication number 20070168903
- Publication date Jul 19, 2007
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for detailed placement of layout objects in a sta...
- Publication number 20070168898
- Publication date Jul 19, 2007
- BLAZE DFM, INC.
- Puneet Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for reshaping metal wires in VLSI design
- Publication number 20070033558
- Publication date Feb 8, 2007
- BLAZE-DFM, INC.
- O. Sam Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Internet telephony through hosts
- Publication number 20070005729
- Publication date Jan 4, 2007
- Johathan Cox
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for topography-aware reticle enhancement
- Publication number 20060110837
- Publication date May 25, 2006
- BLAZE DFM, INC.
- Puneet Gupta
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for correcting a mask design layout
- Publication number 20040237061
- Publication date Nov 25, 2004
- The Regents of the University of California.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floorplan evaluation, global routing, and buffer insertion for inte...
- Publication number 20040117753
- Publication date Jun 17, 2004
- The Regents of the University of California.
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING

Andrew B. Kahng

Person

Patents Grantslast 30 patents

Multi-die IC layout methods with awareness of mix and match die int...

IC layout adjustment method and tool for improving dielectric relia...

Accuracy configurable adders and methods

Gate-length biasing for digital circuit optimization

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Layout decomposition for double patterning lithography

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Layout decomposition for double patterning lithography

Methods for gate-length biasing using annotation data

Gate-length biasing for digital circuit optimization

Tool for modifying mask design layout

Internet telephony through hosts

Method and system for wafer topography-aware integrated circuit des...

Method and apparatus for detecting lithographic hotspots in a circu...

Method, apparatus and system for designing an integrated circuit in...

System and method for performing transistor-level static performanc...

Method of designing a digital circuit by correlating different stat...

Method and system for topography-aware reticle enhancement

Arrangement of fill unit elements in an integrated circuit intercon...

Method and system for finding an equivalent circuit representation...

Method and system for reshaping a transistor gate in an integrated...

Method and system for integrated circuit optimization by using an o...

Layout description having enhanced fill annotation

Method and system for placing layout objects in a standard-cell layout

System and method for varying the starting conditions for a resolut...

Method for correcting a mask design layout

Patents Applicationslast 30 patents

INTEGRATED-CIRCUIT GLOBAL ROUTING METHOD

MULTI-DIE IC LAYOUT METHODS WITH AWARENESS OF MIX AND MATCH DIE INT...

IC LAYOUT ADJUSTMENT METHOD AND TOOL FOR IMPROVING DIELECTRIC RELIA...

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

Gate-Length Biasing for Digital Circuit Optimization

ACCURACY CONFIGURABLE ADDERS AND METHODS

Standard Cells having transistors annotated for gate-length biasing

LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY

METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING

TOOL FOR MODIFYING MASK DESIGN LAYOUT

Method and apparatus for detecting lithographic hotspots

Auxiliary pattern generation for cell-based optical proximity corre...

Method for correcting a mask design layout

Method and system for detailed placement of layout objects in a sta...

Method and system for reshaping metal wires in VLSI design

Internet telephony through hosts

Method and system for topography-aware reticle enhancement

Method for correcting a mask design layout

Floorplan evaluation, global routing, and buffer insertion for inte...