Andrew Chen

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-port bitcell architecture
- Patent number 12,300,310
- Issue date May 13, 2025
- ARM Limited
- Vianney Antoine Choserot
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable scan chain architecture for multi-port memory
- Patent number 12,300,338
- Issue date May 13, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Backside power supply techniques
- Patent number 12,218,664
- Issue date Feb 4, 2025
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal routing techniques
- Patent number 12,164,855
- Issue date Dec 10, 2024
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port memory architecture
- Patent number 12,087,357
- Issue date Sep 10, 2024
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-port circuit architecture
- Patent number 12,066,855
- Issue date Aug 20, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for memory address collision prevention
- Patent number 12,066,926
- Issue date Aug 20, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bitcell architecture using buried metal
- Patent number 11,901,290
- Issue date Feb 13, 2024
- ARM Limited
- Rajiv Kumar Sisodia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wordline modulation techniques
- Patent number 11,900,995
- Issue date Feb 13, 2024
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory testing techniques
- Patent number 11,862,271
- Issue date Jan 2, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frontside-to-backside intermixing architecture for coupling a front...
- Patent number 11,837,543
- Issue date Dec 5, 2023
- ARM Limited
- Andy Wangkun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Data compressor logic circuit
- Patent number 11,831,341
- Issue date Nov 28, 2023
- ARM Limited
- Shardendu Shekhar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wordline driver architecture
- Patent number 11,688,444
- Issue date Jun 27, 2023
- ARM Limited
- Akash Bangalore Srinivasa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with DC biasing
- Patent number 11,676,656
- Issue date Jun 13, 2023
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-tier memory architecture
- Patent number 11,670,363
- Issue date Jun 6, 2023
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Column redundancy techniques
- Patent number 11,664,086
- Issue date May 30, 2023
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible sizing and routing architecture
- Patent number 11,631,439
- Issue date Apr 18, 2023
- ARM Limited
- Sriram Thyagarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Slew-load characterization
- Patent number 11,624,777
- Issue date Apr 11, 2023
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular gated multiplier circuitry and multiplication technique
- Patent number 11,586,445
- Issue date Feb 21, 2023
- ARM Limited
- Shardendu Shekhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
TSV coupled integrated circuits and methods
- Patent number 11,569,219
- Issue date Jan 31, 2023
- ARM Limited
- Rahul Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch circuitry for memory applications
- Patent number 11,568,926
- Issue date Jan 31, 2023
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell architecture
- Patent number 11,557,583
- Issue date Jan 17, 2023
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry apportioning of an integrated circuit
- Patent number 11,532,353
- Issue date Dec 20, 2022
- ARM Limited
- Mudit Bhargava
- G11 - INFORMATION STORAGE
Information Patent Grant
Row redundancy techniques
- Patent number 11,521,703
- Issue date Dec 6, 2022
- ARM Limited
- Amandeep Kaur
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline driver architecture
- Patent number 11,514,979
- Issue date Nov 29, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with pulsed-bias power
- Patent number 11,468,941
- Issue date Oct 11, 2022
- ARM Limited
- Akash Bangalore Srinivasa
- G11 - INFORMATION STORAGE
Information Patent Grant
3D storage architecture with tier-specific controls
- Patent number 11,468,945
- Issue date Oct 11, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Grant
Backside power rail architecture
- Patent number 11,443,777
- Issue date Sep 13, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline decoder circuitry
- Patent number 11,404,096
- Issue date Aug 2, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Buried power rail structure for providing multi-domain power supply...
- Patent number 11,380,384
- Issue date Jul 5, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Systems, Methods, and Devices for a Wordline or a Bitline Formed an...
- Publication number 20250176152
- Publication date May 29, 2025
- Arm Limted
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Dual Wordline Applications in Memory
- Publication number 20250140310
- Publication date May 1, 2025
- ARM Limited
- Vivek Asthana
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE
- Publication number 20250103129
- Publication date Mar 27, 2025
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power-Gate Structure
- Publication number 20250087251
- Publication date Mar 13, 2025
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Row Repair Circuitry
- Publication number 20250087296
- Publication date Mar 13, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Transistor Bitcell Structure
- Publication number 20250078912
- Publication date Mar 6, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Skew Cell Architecture
- Publication number 20250015133
- Publication date Jan 9, 2025
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Port Bitcell Architecture
- Publication number 20240233814
- Publication date Jul 11, 2024
- ARM Limited
- Vianney Antoine Choserot
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Port Circuit Architecture
- Publication number 20240219955
- Publication date Jul 4, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buried Metal Techniques for Memory Applications
- Publication number 20240153551
- Publication date May 9, 2024
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Testing Techniques
- Publication number 20240136006
- Publication date Apr 25, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Port Bitcell Architecture
- Publication number 20240135988
- Publication date Apr 25, 2024
- ARM Limited
- Vianney Antoine Choserot
- G11 - INFORMATION STORAGE
Information Patent Application
Circuitry for Memory Address Collision Prevention
- Publication number 20240012748
- Publication date Jan 11, 2024
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Port Memory Architecture
- Publication number 20230410896
- Publication date Dec 21, 2023
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE
Information Patent Application
Circuits and Methods for I/O Circuitry TSV Coupling
- Publication number 20230411351
- Publication date Dec 21, 2023
- ARM Limited
- Andy Wangkun Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Configurable Scan Chain Architecture for Multi-Port Memory
- Publication number 20230402122
- Publication date Dec 14, 2023
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
TSV Coupled Integrated Circuits and Methods
- Publication number 20230178538
- Publication date Jun 8, 2023
- ARM Limited
- Rahul Mathur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE SIZING AND ROUTING ARCHITECTURE
- Publication number 20230136348
- Publication date May 4, 2023
- ARM Limited
- Sriram Thyagarajan
- G11 - INFORMATION STORAGE
Information Patent Application
Column Redundancy Techniques
- Publication number 20230016339
- Publication date Jan 19, 2023
- ARM Limited
- Yew Keong Chong
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Tier Memory Architecture
- Publication number 20220343970
- Publication date Oct 27, 2022
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Driver Architecture
- Publication number 20220319585
- Publication date Oct 6, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Row Redundancy Techniques
- Publication number 20220319632
- Publication date Oct 6, 2022
- ARM Limited
- Amandeep Kaur
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Modulation Techniques
- Publication number 20220319586
- Publication date Oct 6, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Driver Architecture
- Publication number 20220310144
- Publication date Sep 29, 2022
- ARM Limited
- Akash Bangalore Srinivasa
- G11 - INFORMATION STORAGE
Information Patent Application
Metal Routing Techniques
- Publication number 20220309225
- Publication date Sep 29, 2022
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buried Power Rail Architecture
- Publication number 20220293522
- Publication date Sep 15, 2022
- ARM Limited
- Sriram Thyagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Architecture with Pulsed-Bias Power
- Publication number 20220284942
- Publication date Sep 8, 2022
- ARM Limited
- Akash Bangalore Srinivasa
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Architecture with DC Biasing
- Publication number 20220254411
- Publication date Aug 11, 2022
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Circuitry Apportioning of an Integrated Circuit
- Publication number 20220246206
- Publication date Aug 4, 2022
- ARM Limited
- Mudit Bhargava
- G11 - INFORMATION STORAGE
Information Patent Application
Bitcell Architecture Using Buried Metal
- Publication number 20220223514
- Publication date Jul 14, 2022
- ARM Limited
- Rajiv Kumar Sisodia
- H01 - BASIC ELECTRIC ELEMENTS

Andrew Chen

Person

Patents Grantslast 30 patents

Multi-port bitcell architecture

Configurable scan chain architecture for multi-port memory

Backside power supply techniques

Metal routing techniques

Multi-port memory architecture

Multi-port circuit architecture

Circuitry for memory address collision prevention

Bitcell architecture using buried metal

Wordline modulation techniques

Memory testing techniques

Frontside-to-backside intermixing architecture for coupling a front...

Data compressor logic circuit

Wordline driver architecture

Memory architecture with DC biasing

Multi-tier memory architecture

Column redundancy techniques

Flexible sizing and routing architecture

Slew-load characterization

Modular gated multiplier circuitry and multiplication technique

TSV coupled integrated circuits and methods

Latch circuitry for memory applications

Cell architecture

Circuitry apportioning of an integrated circuit

Row redundancy techniques

Wordline driver architecture

Memory architecture with pulsed-bias power

3D storage architecture with tier-specific controls

Backside power rail architecture

Wordline decoder circuitry

Buried power rail structure for providing multi-domain power supply...

Patents Applicationslast 30 patents

Systems, Methods, and Devices for a Wordline or a Bitline Formed an...

Dual Wordline Applications in Memory

POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE

Power-Gate Structure

Row Repair Circuitry

Multi-Transistor Bitcell Structure

Skew Cell Architecture

Multi-Port Bitcell Architecture

Multi-Port Circuit Architecture

Buried Metal Techniques for Memory Applications

Memory Testing Techniques

Multi-Port Bitcell Architecture

Circuitry for Memory Address Collision Prevention

Multi-Port Memory Architecture

Circuits and Methods for I/O Circuitry TSV Coupling

Configurable Scan Chain Architecture for Multi-Port Memory

TSV Coupled Integrated Circuits and Methods

FLEXIBLE SIZING AND ROUTING ARCHITECTURE

Column Redundancy Techniques

Multi-Tier Memory Architecture

Wordline Driver Architecture

Row Redundancy Techniques

Wordline Modulation Techniques

Wordline Driver Architecture

Metal Routing Techniques

Buried Power Rail Architecture

Memory Architecture with Pulsed-Bias Power

Memory Architecture with DC Biasing

Circuitry Apportioning of an Integrated Circuit

Bitcell Architecture Using Buried Metal