Andrew J. Beaumont-Smith

Person

Cambridge, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,174,785
- Issue date Dec 24, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,135,681
- Issue date Nov 5, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor prefetcher
- Patent number 12,050,918
- Issue date Jul 30, 2024
- Apple Inc.
- Brandon H. Dwiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor register renaming using registers associated with an in...
- Patent number 11,775,301
- Issue date Oct 3, 2023
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,768,690
- Issue date Sep 26, 2023
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor prefetcher
- Patent number 11,755,333
- Issue date Sep 12, 2023
- Apple Inc.
- Brandon H. Dwiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug trace of cache memory requests
- Patent number 11,740,993
- Issue date Aug 29, 2023
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor synchronizing instruction suppression
- Patent number 11,650,825
- Issue date May 16, 2023
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 11,429,555
- Issue date Aug 30, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor synchronizing instruction suppression
- Patent number 11,249,766
- Issue date Feb 15, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor context priority
- Patent number 11,210,104
- Issue date Dec 28, 2021
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessor with distributed register
- Patent number 10,846,091
- Issue date Nov 24, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computation engine with extract instructions to minimize memory access
- Patent number 10,831,488
- Issue date Nov 10, 2020
- Apple Inc.
- Eric Bainville
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining the integrity of an execution return address stack
- Patent number 9,354,886
- Issue date May 31, 2016
- Apple Inc.
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction type issue throttling upon reaching threshold by adjust...
- Patent number 9,009,451
- Issue date Apr 14, 2015
- Apple Inc.
- Daniel C. Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing update training of first predictor with mismatching seco...
- Patent number 8,959,320
- Issue date Feb 17, 2015
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,566,528
- Issue date Oct 22, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect branch target predictor that prevents speculation if mispr...
- Patent number 8,555,040
- Issue date Oct 8, 2013
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor employing split scheduler in which near, low latency oper...
- Patent number 8,364,936
- Issue date Jan 29, 2013
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combining write buffer with dynamically adjustable flush metrics
- Patent number 8,352,685
- Issue date Jan 8, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store hit load predictor
- Patent number 8,285,947
- Issue date Oct 9, 2012
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor employing split scheduler in which near, low latency oper...
- Patent number 8,255,671
- Issue date Aug 28, 2012
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of a microprocessor subtraction-division floating...
- Patent number 7,127,483
- Issue date Oct 24, 2006
- Hewlett-Packard Development Company, L.P.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Coprocessor Prefetcher
- Publication number 20240095037
- Publication date Mar 21, 2024
- Apple Inc.
- Brandon H. Dwiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Register Renaming
- Publication number 20240045680
- Publication date Feb 8, 2024
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug Trace of Cache Memory Requests
- Publication number 20230418724
- Publication date Dec 28, 2023
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Register Renaming
- Publication number 20230095072
- Publication date Mar 30, 2023
- Apple Inc.
- Ran Aharon Chachick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Prefetcher
- Publication number 20230092898
- Publication date Mar 23, 2023
- Apple Inc.
- Brandon H. Dwiel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug Trace of Cache Memory Requests
- Publication number 20230061419
- Publication date Mar 2, 2023
- Apple Inc.
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220358082
- Publication date Nov 10, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20220350776
- Publication date Nov 3, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Synchronizing Instruction Suppression
- Publication number 20220214887
- Publication date Jul 7, 2022
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Context Priority
- Publication number 20220083343
- Publication date Mar 17, 2022
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20200272597
- Publication date Aug 27, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor with Distributed Register
- Publication number 20200272467
- Publication date Aug 27, 2020
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Outer Product Engine
- Publication number 20180074824
- Publication date Mar 15, 2018
- Apple Inc.
- Ali Sazegari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS
- Publication number 20130151823
- Publication date Jun 13, 2013
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING THE INTEGRITY OF AN EXECUTION RETURN ADDRESS STACK
- Publication number 20130138931
- Publication date May 30, 2013
- Ramesh B. Gunna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR INSTRUCTION ISSUE THROTTLING
- Publication number 20130111191
- Publication date May 2, 2013
- Daniel C. Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20130103906
- Publication date Apr 25, 2013
- Apple Inc.
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split Scheduler
- Publication number 20120290818
- Publication date Nov 15, 2012
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combining Write Buffer with Dynamically Adjustable Flush Metrics
- Publication number 20120047332
- Publication date Feb 23, 2012
- Peter J. Bannon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indirect Branch Target Predictor that Prevents Speculation if Mispr...
- Publication number 20110289300
- Publication date Nov 24, 2011
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Store Hit Load Predictor
- Publication number 20100205384
- Publication date Aug 12, 2010
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split Scheduler
- Publication number 20100162262
- Publication date Jun 24, 2010
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor floating point divider
- Publication number 20030135531
- Publication date Jul 17, 2003
- Andrew J. Beaumont-Smith
- G06 - COMPUTING CALCULATING COUNTING

Andrew J. Beaumont-Smith

Person

Patents Grantslast 30 patents

Coprocessors with bypass optimization, variable grid architecture,...

Coprocessors with bypass optimization, variable grid architecture,...

Coprocessor prefetcher

Coprocessor register renaming using registers associated with an in...

Coprocessor context priority

Coprocessor prefetcher

Debug trace of cache memory requests

Coprocessor synchronizing instruction suppression

Coprocessors with bypass optimization, variable grid architecture,...

Coprocessor synchronizing instruction suppression

Coprocessor context priority

Coprocessor with distributed register

Computation engine with extract instructions to minimize memory access

Maintaining the integrity of an execution return address stack

Instruction type issue throttling upon reaching threshold by adjust...

Preventing update training of first predictor with mismatching seco...

Combining write buffer with dynamically adjustable flush metrics

Indirect branch target predictor that prevents speculation if mispr...

Processor employing split scheduler in which near, low latency oper...

Combining write buffer with dynamically adjustable flush metrics

Store hit load predictor

Processor employing split scheduler in which near, low latency oper...

Method and system of a microprocessor subtraction-division floating...

Patents Applicationslast 30 patents

Coprocessor Prefetcher

Coprocessor Register Renaming

Debug Trace of Cache Memory Requests

Coprocessor Register Renaming

Coprocessor Prefetcher

Debug Trace of Cache Memory Requests

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessor Synchronizing Instruction Suppression

Coprocessor Context Priority

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

Coprocessor with Distributed Register

Outer Product Engine

NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS

MAINTAINING THE INTEGRITY OF AN EXECUTION RETURN ADDRESS STACK

PROCESSOR INSTRUCTION ISSUE THROTTLING

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Split Scheduler

Combining Write Buffer with Dynamically Adjustable Flush Metrics

Indirect Branch Target Predictor that Prevents Speculation if Mispr...

Store Hit Load Predictor

Split Scheduler

Microprocessor floating point divider