Andrew Leaver

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing compilation using multiple desi...
- Patent number 9,122,826
- Issue date Sep 1, 2015
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
M/A for performing incremental compilation using top-down and botto...
- Patent number 8,589,838
- Issue date Nov 19, 2013
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing incremental compilation using t...
- Patent number 8,250,505
- Issue date Aug 21, 2012
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Tracing and reporting registers removed during synthesis
- Patent number 8,166,427
- Issue date Apr 24, 2012
- Altera Corporation
- Swatiben Ruturaj Pathak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection and input/output resources for programmable logic i...
- Patent number 7,839,167
- Issue date Nov 23, 2010
- Altera Corporation
- Tony Ngai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing incremental compilation using t...
- Patent number 7,669,157
- Issue date Feb 23, 2010
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection and input/output resources for programmable logic i...
- Patent number 7,492,188
- Issue date Feb 17, 2009
- Altera Corporation
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental compilation
- Patent number 7,464,362
- Issue date Dec 9, 2008
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection and input/output resources for programmable logic i...
- Patent number 6,989,689
- Issue date Jan 24, 2006
- Altera Corporation
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection and input/output resources for programmable logic i...
- Patent number 6,894,533
- Issue date May 17, 2005
- Altera Corporation
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection and input/output resources for programmable logic i...
- Patent number 6,407,576
- Issue date Jun 18, 2002
- Altera Corporation
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping heterogeneous logic elements in a programmable logic device
- Patent number 6,195,788
- Issue date Feb 27, 2001
- Altera Corporation
- Andrew Leaver
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC I...
- Publication number 20090289660
- Publication date Nov 26, 2009
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection and input/output resources for programmable logic i...
- Publication number 20080074143
- Publication date Mar 27, 2008
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection and input/output resources for programmable logic i...
- Publication number 20040251930
- Publication date Dec 16, 2004
- Altera Corporation
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection and input/output resources for programmable logic i...
- Publication number 20030210073
- Publication date Nov 13, 2003
- Tony Ngai
- G06 - COMPUTING CALCULATING COUNTING

Andrew Leaver

Person

Patents Grantslast 30 patents

Method and apparatus for performing compilation using multiple desi...

M/A for performing incremental compilation using top-down and botto...

Method and apparatus for performing incremental compilation using t...

Tracing and reporting registers removed during synthesis

Interconnection and input/output resources for programmable logic i...

Method and apparatus for performing incremental compilation using t...

Interconnection and input/output resources for programmable logic i...

Method and apparatus for performing incremental compilation

Interconnection and input/output resources for programmable logic i...

Interconnection and input/output resources for programmable logic i...

Interconnection and input/output resources for programmable logic i...

Mapping heterogeneous logic elements in a programmable logic device

Patents Applicationslast 30 patents

INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC I...

Interconnection and input/output resources for programmable logic i...

Interconnection and input/output resources for programmable logic i...

Interconnection and input/output resources for programmable logic i...