Andrew M. Draper

Person

Chesham, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Seamless firmware update mechanism
- Patent number 12,189,775
- Issue date Jan 7, 2025
- Intel Corporation
- Ned M. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-device bitstream validation
- Patent number 11,562,101
- Issue date Jan 24, 2023
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Side-channel attack resistant fuse programming
- Patent number 11,281,383
- Issue date Mar 22, 2022
- Intel Corporation
- Ting Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional partial reconfiguration of a programmable device
- Patent number 10,659,052
- Issue date May 19, 2020
- Intel Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing a JTAG interface among multiple partitions
- Patent number 10,444,283
- Issue date Oct 15, 2019
- Intel Corporation
- Yi Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining reconfigurable partitions in a programmable device
- Patent number 10,223,014
- Issue date Mar 5, 2019
- Intel Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional partial reconfiguration of a programmable device
- Patent number 10,218,359
- Issue date Feb 26, 2019
- Intel Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and methods for debug connectivity discovery
- Patent number 9,404,968
- Issue date Aug 2, 2016
- Altera Corporation
- Andrew Draper
- G01 - MEASURING TESTING
Information Patent Grant
Using FPGA partial reconfiguration for codec applications
- Patent number 9,191,617
- Issue date Nov 17, 2015
- Altera Corporation
- Russell A. James
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Booting mechanism for FPGA-based embedded system
- Patent number 8,412,918
- Issue date Apr 2, 2013
- Altera Corporation
- Timothy P. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with dual-port SRAM for programmable logic
- Patent number 8,190,828
- Issue date May 29, 2012
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible on-chip datapath interface having first and second compone...
- Patent number 8,069,286
- Issue date Nov 29, 2011
- Altera Corporation
- Kent Orthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible on-chip datapath interface for facilitating communication...
- Patent number 7,844,761
- Issue date Nov 30, 2010
- Altera Corporation
- Kent Orthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Booting mechanism for FPGA-based embedded system
- Patent number 7,822,958
- Issue date Oct 26, 2010
- Altera Corporation
- Timothy P. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for handling reset events in a bus bridge
- Patent number 7,657,689
- Issue date Feb 2, 2010
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring an embedded processor operating system
- Patent number 7,584,348
- Issue date Sep 1, 2009
- Altera Corporation
- Andrew Draper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split filtering in multilayer systems
- Patent number 7,549,004
- Issue date Jun 16, 2009
- Altera Corporation
- Fabio P Sousa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with dual-port SRAM for programmable logic
- Patent number 7,546,424
- Issue date Jun 9, 2009
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for debugging a system with a hung data bus
- Patent number 7,412,624
- Issue date Aug 12, 2008
- Altera Corporation
- Andrew Draper
- G01 - MEASURING TESTING
Information Patent Grant
Embedded processor with watchdog timer for programmable logic
- Patent number 7,350,178
- Issue date Mar 25, 2008
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring both a programmable logic device and its embedded logic...
- Patent number 7,343,483
- Issue date Mar 11, 2008
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with watchdog timer for programmable logic
- Patent number 7,340,596
- Issue date Mar 4, 2008
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital data error insertion methods and apparatus
- Patent number 7,321,996
- Issue date Jan 22, 2008
- Altera Corporation
- Andrew Draper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor system
- Patent number 7,263,623
- Issue date Aug 28, 2007
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching data based on predetermined criteria
- Patent number 7,249,222
- Issue date Jul 24, 2007
- Altera Corporation
- Andrew Bellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded processor with dual-port SRAM for programmable logic
- Patent number 7,096,324
- Issue date Aug 22, 2006
- Altera Corporation
- Roger May
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface controller using JTAG scan chain
- Patent number 7,078,929
- Issue date Jul 18, 2006
- Altera Corporation
- Andrew Draper
- G01 - MEASURING TESTING
Information Patent Grant
Distributed bus structure
- Patent number 7,064,578
- Issue date Jun 20, 2006
- Altera Corporation
- Andrew Crosland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
JTAG mirroring circuitry and methods
- Patent number 6,961,884
- Issue date Nov 1, 2005
- Altera Corporation
- Andrew M. Draper
- G01 - MEASURING TESTING
Information Patent Grant
Address decoder for programmable logic device
- Patent number 6,937,061
- Issue date Aug 30, 2005
- Altera Corporation
- Andrew Crosland
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE CHANNEL DIRECT ACCESS MEMORY-BASED CONFIGURATION SYSTEM
- Publication number 20240004810
- Publication date Jan 4, 2024
- Intel Corporation
- Gary Brian Wallichs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEAMLESS FIRMWARE UPDATE MECHANISM
- Publication number 20220245252
- Publication date Aug 4, 2022
- Intel Corporation
- Ned M. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for enabling Multiple Return Material Authoriz...
- Publication number 20210012855
- Publication date Jan 14, 2021
- Sankaran M. Menon
- G11 - INFORMATION STORAGE
Information Patent Application
REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE
- Publication number 20190199354
- Publication date Jun 27, 2019
- Intel Corproratlon
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING RECONFIGURABLE PARTITIONS IN A PROGRAMMABLE DEVICE
- Publication number 20190095113
- Publication date Mar 28, 2019
- Intel Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEVICE BITSTREAM VALIDATION
- Publication number 20190050604
- Publication date Feb 14, 2019
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE DEVICE AUTHENTICATION DECRYPTION
- Publication number 20190050603
- Publication date Feb 14, 2019
- Intel Corporation
- Sean R. Atsatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDE-CHANNEL ATTACK RESISTANT FUSE PROGRAMMING
- Publication number 20190042118
- Publication date Feb 7, 2019
- Intel Corporation
- Ting Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE
- Publication number 20190007050
- Publication date Jan 3, 2019
- Intel Corproration
- Sean R. Atsatt
- H03 - BASIC ELECTRONIC CIRCUITRY

Andrew M. Draper

Person

Patents Grantslast 30 patents

Seamless firmware update mechanism

On-device bitstream validation

Side-channel attack resistant fuse programming

Regional partial reconfiguration of a programmable device

Sharing a JTAG interface among multiple partitions

Maintaining reconfigurable partitions in a programmable device

Regional partial reconfiguration of a programmable device

System and methods for debug connectivity discovery

Using FPGA partial reconfiguration for codec applications

Booting mechanism for FPGA-based embedded system

Embedded processor with dual-port SRAM for programmable logic

Flexible on-chip datapath interface having first and second compone...

Flexible on-chip datapath interface for facilitating communication...

Booting mechanism for FPGA-based embedded system

Methods and apparatus for handling reset events in a bus bridge

Techniques for configuring an embedded processor operating system

Split filtering in multilayer systems

Embedded processor with dual-port SRAM for programmable logic

Methods and apparatus for debugging a system with a hung data bus

Embedded processor with watchdog timer for programmable logic

Configuring both a programmable logic device and its embedded logic...

Embedded processor with watchdog timer for programmable logic

Digital data error insertion methods and apparatus

Microprocessor system

Prefetching data based on predetermined criteria

Embedded processor with dual-port SRAM for programmable logic

Interface controller using JTAG scan chain

Distributed bus structure

JTAG mirroring circuitry and methods

Address decoder for programmable logic device

Patents Applicationslast 30 patents

MULTIPLE CHANNEL DIRECT ACCESS MEMORY-BASED CONFIGURATION SYSTEM

SEAMLESS FIRMWARE UPDATE MECHANISM

Method and Apparatus for enabling Multiple Return Material Authoriz...

REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE

MAINTAINING RECONFIGURABLE PARTITIONS IN A PROGRAMMABLE DEVICE

ON-DEVICE BITSTREAM VALIDATION

PROGRAMMABLE DEVICE AUTHENTICATION DECRYPTION

SIDE-CHANNEL ATTACK RESISTANT FUSE PROGRAMMING

REGIONAL PARTIAL RECONFIGURATION OF A PROGRAMMABLE DEVICE