Andrew Mark Chapman

Person

Milton, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Post-CTS insertion delay and skew target reformulation of clock tree
- Patent number 12,061,857
- Issue date Aug 13, 2024
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-CTS clock tree restructuring
- Patent number 11,620,428
- Issue date Apr 4, 2023
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-CTS clock tree restructuring with ripple move
- Patent number 11,354,479
- Issue date Jun 7, 2022
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying route topology to fix clock tree violations
- Patent number 10,963,617
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Runtime efficient circuit placement search location selection
- Patent number 10,936,783
- Issue date Mar 2, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock gate placement with data path awareness
- Patent number 10,885,250
- Issue date Jan 5, 2021
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree optimization by moving instances toward core route
- Patent number 10,769,345
- Issue date Sep 8, 2020
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree wirelength reduction based on a target offset in connect...
- Patent number 10,740,530
- Issue date Aug 11, 2020
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING

Andrew Mark Chapman

Person

Patents Grantslast 30 patents

Post-CTS insertion delay and skew target reformulation of clock tree

Post-CTS clock tree restructuring

Post-CTS clock tree restructuring with ripple move

Modifying route topology to fix clock tree violations

Runtime efficient circuit placement search location selection

Clock gate placement with data path awareness

Clock tree optimization by moving instances toward core route

Clock tree wirelength reduction based on a target offset in connect...