Andy Wottreng

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Operating system management of address-translation-related data str...
- Patent number 8,645,667
- Issue date Feb 4, 2014
- International Business Machines Corporation
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for handling a cache miss
- Patent number 8,589,630
- Issue date Nov 19, 2013
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating system management of address-translation-related data str...
- Patent number 8,589,657
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for handling a cache miss
- Patent number 8,327,075
- Issue date Dec 4, 2012
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Loading entries into a TLB in hardware via indirect TLB entries
- Patent number 8,296,547
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Timothy H. Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms for priority control in resource allocation
- Patent number 8,180,941
- Issue date May 15, 2012
- International Business Machines Corporation
- Wen-Tzer T. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for allowing uninterrupted address translation...
- Patent number 8,127,082
- Issue date Feb 28, 2012
- International Business Machines Corporation
- Chad B. McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to bypass cache levels in a cache coherent system
- Patent number 8,108,617
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Timothy H. Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-cost cache coherency for accelerators
- Patent number 8,103,835
- Issue date Jan 24, 2012
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using an index value located on a page table to index page attributes
- Patent number 8,028,118
- Issue date Sep 27, 2011
- Internation Business Machines Corporation
- Timothy Hume Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing accelerator support in a bus pro...
- Patent number 7,827,343
- Issue date Nov 2, 2010
- International Business Machines Corporation
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-cost cache coherency for accelerators
- Patent number 7,814,279
- Issue date Oct 12, 2010
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing conditional packet alterations based on transmit port
- Patent number 7,757,006
- Issue date Jul 13, 2010
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
I/O address translation method for specifying a relaxed ordering fo...
- Patent number 7,721,023
- Issue date May 18, 2010
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo LRU algorithm for hint-locking during software and hardware...
- Patent number 7,716,423
- Issue date May 11, 2010
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priority control in resource allocation for low request rate, laten...
- Patent number 7,631,131
- Issue date Dec 8, 2009
- International Business Machines Corporation
- Wen-Tzer T. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronizing a plurality of processors
- Patent number 7,552,269
- Issue date Jun 23, 2009
- International Business Machines Corporation
- Steven Mark Thurber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling concurrent address translation cache misses and hits under...
- Patent number 7,539,840
- Issue date May 26, 2009
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of resource allocation using an access control mechanism
- Patent number 7,530,068
- Issue date May 5, 2009
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing conditional packet alterations based on transmit port
- Patent number 7,475,161
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Invalidating multiple address cache entries
- Patent number 7,472,227
- Issue date Dec 30, 2008
- International Business Machines Corporation
- Chad B. McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional hardware scan dump data capture
- Patent number 6,880,113
- Issue date Apr 12, 2005
- International Business Machines Corporation
- Gary D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to monitor the run state of a multi-partitione...
- Patent number 6,711,700
- Issue date Mar 23, 2004
- International Business Machines Corporation
- Troy David Armstrong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for selecting thread switch events in a multit...
- Patent number 6,697,935
- Issue date Feb 24, 2004
- International Business Machines Corporation
- John Michael Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread switch control in a multithreaded processor system
- Patent number 6,567,839
- Issue date May 20, 2003
- International Business Machines Corporation
- John Michael Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for memory self-timed refresh for reduced power c...
- Patent number 6,334,167
- Issue date Dec 25, 2001
- International Business Machines Corporation
- Edward T. Gerchman
- G11 - INFORMATION STORAGE
Information Patent Grant
Altering thread priorities in a multithreaded processor
- Patent number 6,212,544
- Issue date Apr 3, 2001
- International Business Machines Corporation
- John Michael Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to guarantee forward progress in execution of...
- Patent number 6,105,051
- Issue date Aug 15, 2000
- International Business Machines Corporation
- John Michael Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Background completion of instruction and associated fetch request i...
- Patent number 6,088,788
- Issue date Jul 11, 2000
- International Business Machines Corporation
- John M. Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to force a thread switch in a multithreaded pr...
- Patent number 6,076,157
- Issue date Jun 13, 2000
- International Business Machines Corporation
- John Michael Borkenhagen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Operating System Management of Address-Translation-Related Data Str...
- Publication number 20120284465
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR HANDLING A CACHE MISS
- Publication number 20120272009
- Publication date Oct 25, 2012
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Operating System Management of Address-Translation-Related Data Str...
- Publication number 20120173842
- Publication date Jul 5, 2012
- International Business Machines Corporation
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-COST CACHE COHERENCY FOR ACCELERATORS
- Publication number 20110029738
- Publication date Feb 3, 2011
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanisms for Priority Control in Resource Allocation
- Publication number 20100146512
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Wen-Tzer T. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES
- Publication number 20100058026
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Timothy H. Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to Bypass Cache Levels in a Cache Coherent System
- Publication number 20090204769
- Publication date Aug 13, 2009
- Timothy H. Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER...
- Publication number 20090187695
- Publication date Jul 23, 2009
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indexing Page Attributes
- Publication number 20090150642
- Publication date Jun 11, 2009
- Timothy Hume Heil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT
- Publication number 20090144452
- Publication date Jun 4, 2009
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING ACCELERATOR SUPPORT IN A BUS PRO...
- Publication number 20090083471
- Publication date Mar 26, 2009
- Bradly George Frey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Synchronizing a Plurality of Processors
- Publication number 20080172507
- Publication date Jul 17, 2008
- Steven Mark Thurber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Handling Concurrent Address Translation Ca...
- Publication number 20070283121
- Publication date Dec 6, 2007
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Assisted Exception for Software Miss Handling of an I/O Ad...
- Publication number 20070260754
- Publication date Nov 8, 2007
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-cost cache coherency for accelerators
- Publication number 20070226424
- Publication date Sep 27, 2007
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pseudo LRU algorithm for hint-locking during software and hardware...
- Publication number 20070186046
- Publication date Aug 9, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O address translation blocking in a secure system during power-on...
- Publication number 20070180269
- Publication date Aug 2, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for allowing uninterrupted address translation...
- Publication number 20070180195
- Publication date Aug 2, 2007
- International Business Machines Corporation
- Chad B. McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for handling a cache miss
- Publication number 20070136532
- Publication date Jun 14, 2007
- International Business Machines Corporation
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O address translation apparatus and method for specifying a relax...
- Publication number 20070130372
- Publication date Jun 7, 2007
- John D. Irish
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Priority control in resource allocation for low request rate, laten...
- Publication number 20070101033
- Publication date May 3, 2007
- Wen-Tzer T. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for invalidating multiple address cache entries
- Publication number 20070038797
- Publication date Feb 15, 2007
- International Business Machines Corporation
- Chad B. McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of resource allocation using an access control mechanism
- Publication number 20050138621
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Scott Douglas Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus and computer program product for implementing con...
- Publication number 20050055462
- Publication date Mar 10, 2005
- International Business Machines Corporation
- Kerry Christopher Imming
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Conditional hardware scan dump data capture
- Publication number 20020166083
- Publication date Nov 7, 2002
- International Business Machines Corporation
- Gary D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to monitor the run state of a multi-partitione...
- Publication number 20020156939
- Publication date Oct 24, 2002
- International Business Machines Corporation
- Troy David Armstrong
- G06 - COMPUTING CALCULATING COUNTING

Andy Wottreng

Person

Patents Grantslast 30 patents

Operating system management of address-translation-related data str...

Methods and apparatus for handling a cache miss

Operating system management of address-translation-related data str...

Methods and apparatus for handling a cache miss

Loading entries into a TLB in hardware via indirect TLB entries

Mechanisms for priority control in resource allocation

Method and apparatus for allowing uninterrupted address translation...

Method to bypass cache levels in a cache coherent system

Low-cost cache coherency for accelerators

Using an index value located on a page table to index page attributes

Method and apparatus for providing accelerator support in a bus pro...

Low-cost cache coherency for accelerators

Implementing conditional packet alterations based on transmit port

I/O address translation method for specifying a relaxed ordering fo...

Pseudo LRU algorithm for hint-locking during software and hardware...

Priority control in resource allocation for low request rate, laten...

Synchronizing a plurality of processors

Handling concurrent address translation cache misses and hits under...

Method of resource allocation using an access control mechanism

Implementing conditional packet alterations based on transmit port

Invalidating multiple address cache entries

Conditional hardware scan dump data capture

Method and apparatus to monitor the run state of a multi-partitione...

Method and apparatus for selecting thread switch events in a multit...

Thread switch control in a multithreaded processor system

System and method for memory self-timed refresh for reduced power c...

Altering thread priorities in a multithreaded processor

Apparatus and method to guarantee forward progress in execution of...

Background completion of instruction and associated fetch request i...

Method and apparatus to force a thread switch in a multithreaded pr...

Patents Applicationslast 30 patents

Operating System Management of Address-Translation-Related Data Str...

METHODS AND APPARATUS FOR HANDLING A CACHE MISS

Operating System Management of Address-Translation-Related Data Str...

LOW-COST CACHE COHERENCY FOR ACCELERATORS

Mechanisms for Priority Control in Resource Allocation

LOADING ENTRIES INTO A TLB IN HARDWARE VIA INDIRECT TLB ENTRIES

Method to Bypass Cache Levels in a Cache Coherent System

HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER...

Indexing Page Attributes

IMPLEMENTING CONDITIONAL PACKET ALTERATIONS BASED ON TRANSMIT PORT

METHOD AND APPARATUS FOR PROVIDING ACCELERATOR SUPPORT IN A BUS PRO...

Methods and Apparatus for Synchronizing a Plurality of Processors

Method and Apparatus for Handling Concurrent Address Translation Ca...

Hardware Assisted Exception for Software Miss Handling of an I/O Ad...

Low-cost cache coherency for accelerators

Pseudo LRU algorithm for hint-locking during software and hardware...

I/O address translation blocking in a secure system during power-on...

Method and apparatus for allowing uninterrupted address translation...

Methods and apparatus for handling a cache miss

I/O address translation apparatus and method for specifying a relax...

Priority control in resource allocation for low request rate, laten...

Methods and apparatus for invalidating multiple address cache entries

Method of resource allocation using an access control mechanism

Method, apparatus and computer program product for implementing con...

Conditional hardware scan dump data capture

Method and apparatus to monitor the run state of a multi-partitione...