Angad Narang

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Rancho Cordova, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for prefetching data into cache
- Patent number 6,643,745
- Issue date Nov 4, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache structure for temporal and non-temporal instructions
- Patent number 6,584,547
- Issue date Jun 24, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for load buffers
- Patent number 6,526,499
- Issue date Feb 25, 2003
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for senior loads
- Patent number 6,216,215
- Issue date Apr 10, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared cache structure for temporal and non-temporal information us...
- Patent number 6,202,129
- Issue date Mar 13, 2001
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimizing write combining performance in a s...
- Patent number 6,122,715
- Issue date Sep 19, 2000
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Shared cache structure for temporal and non-temporal instructions
- Publication number 20020007441
- Publication date Jan 17, 2002
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for senior loads
- Publication number 20010001153
- Publication date May 10, 2001
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING