Angela Krstic

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Germantown, MD, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for generating design constraints
- Patent number 8,627,249
- Issue date Jan 7, 2014
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying multiple constraints for circuit designs
- Patent number 8,209,648
- Issue date Jun 26, 2012
- Cadence Design Systems, Inc.
- Shan-Chyun Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for generating design constraints
- Patent number 7,962,886
- Issue date Jun 14, 2011
- Cadence Design Systems, Inc.
- Manish Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing high speed VLSI devices using slower...
- Patent number 6,345,373
- Issue date Feb 5, 2002
- The University of California
- Srimat T. Chakradhar
- G01 - MEASURING TESTING
Information Patent Grant
Identification and test generation for primitive faults
- Patent number 6,018,813
- Issue date Jan 25, 2000
- NEC USA, Inc.
- Srimat T. Chakradhar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Method for test application and test content generation for AC faul...
- Publication number 20050102594
- Publication date May 12, 2005
- The Regents of the University of California.
- Sujit Dey
- G01 - MEASURING TESTING