Anh Phan

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 12,148,806
- Issue date Nov 19, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contacts for semiconductor devices
- Patent number 12,080,605
- Issue date Sep 3, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation wall stressor structures to improve channel stress and th...
- Patent number 12,033,896
- Issue date Jul 9, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial layer with substantially parallel sides
- Patent number 12,020,929
- Issue date Jun 25, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leave-behind protective layer having secondary purpose
- Patent number 11,996,408
- Issue date May 28, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked forksheet transistors
- Patent number 11,996,411
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 11,942,416
- Issue date Mar 26, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 11,916,118
- Issue date Feb 27, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked trigate transistors with dielectric isolation and process f...
- Patent number 11,894,372
- Issue date Feb 6, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization structures for stacked device connectivity and their...
- Patent number 11,869,894
- Issue date Jan 9, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 11,830,933
- Issue date Nov 28, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall interconnect metallization structures for integrated circu...
- Patent number 11,776,898
- Issue date Oct 3, 2023
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 11,764,263
- Issue date Sep 19, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an oxide volume within a fin
- Patent number 11,764,104
- Issue date Sep 19, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 11,742,346
- Issue date Aug 29, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked transistor devices with isolation wall structure...
- Patent number 11,699,637
- Issue date Jul 11, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors having device strata with different channel widths
- Patent number 11,676,966
- Issue date Jun 13, 2023
- Intel Corporation
- Gilbert W. Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 11,646,352
- Issue date May 9, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V source/drain in top NMOS transistors for low temperature stac...
- Patent number 11,640,961
- Issue date May 2, 2023
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for forming gate structures for transistors arranged in...
- Patent number 11,616,060
- Issue date Mar 28, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical diode in stacked transistor architecture
- Patent number 11,616,056
- Issue date Mar 28, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuits with stacked transistors
- Patent number 11,605,565
- Issue date Mar 14, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked trigate transistors with dielectric isolation between first...
- Patent number 11,594,533
- Issue date Feb 28, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors with different gate lengths in different device...
- Patent number 11,573,798
- Issue date Feb 7, 2023
- Intel Corporation
- Aaron D. Lilak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked transistors with dielectric between channels of different d...
- Patent number 11,552,104
- Issue date Jan 10, 2023
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors on heterogeneous bonding layers
- Patent number 11,532,719
- Issue date Dec 20, 2022
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked CMOS with upfront M0 interconnect
- Patent number 11,482,621
- Issue date Oct 25, 2022
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contacts for semiconductor devices
- Patent number 11,437,283
- Issue date Sep 6, 2022
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors stacked on front-end p-type transistors
- Patent number 11,437,405
- Issue date Sep 6, 2022
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240371700
- Publication date Nov 7, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FORKSHEET TRANSISTORS
- Publication number 20240234422
- Publication date Jul 11, 2024
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS
- Publication number 20240186398
- Publication date Jun 6, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...
- Publication number 20240162141
- Publication date May 16, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20240145557
- Publication date May 2, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240047559
- Publication date Feb 8, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20230377947
- Publication date Nov 23, 2023
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20230369399
- Publication date Nov 16, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN RE...
- Publication number 20230352481
- Publication date Nov 2, 2023
- Intel Corporation
- AARON D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20230238436
- Publication date Jul 27, 2023
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS F...
- Publication number 20230170350
- Publication date Jun 1, 2023
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION...
- Publication number 20230090092
- Publication date Mar 23, 2023
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20220352032
- Publication date Nov 3, 2022
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION WALL STRESSOR STRUCTURES TO IMPROVE CHANNEL STRESS AND TH...
- Publication number 20220352029
- Publication date Nov 3, 2022
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METALLIZATION STRUCTURES FOR STACKED DEVICE CONNECTIVITY AND THEIR...
- Publication number 20220344376
- Publication date Oct 27, 2022
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE
- Publication number 20220246608
- Publication date Aug 4, 2022
- Intel Corporation
- AARON D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY STACKED TRANSISTOR DEVICES WITH ISOLATION WALL STRUCTURE...
- Publication number 20220102246
- Publication date Mar 31, 2022
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FORKSHEET TRANSISTORS
- Publication number 20210407999
- Publication date Dec 30, 2021
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTOR STRUCTURES WITH ASYMMETRICAL TERMINAL INTERCONNECTS
- Publication number 20210305098
- Publication date Sep 30, 2021
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTORS WITH SI PMOS AND HIGH MOBILITY THIN FILM TRANSI...
- Publication number 20210091080
- Publication date Mar 25, 2021
- Intel Corporation
- Gilbert DEWEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V SOURCE/DRAIN IN TOP NMOS TRANSISTORS FOR LOW TEMPERATURE STAC...
- Publication number 20210057413
- Publication date Feb 25, 2021
- Intel Corporation
- Gilbert DEWEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS F...
- Publication number 20200411511
- Publication date Dec 31, 2020
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES WITH A LOGIC REGION BETWEEN MEMORY REGIONS
- Publication number 20200411428
- Publication date Dec 31, 2020
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES WITH AIR GAPPING BETWEEN STACKED TRANSISTORS AND PROCESS FO...
- Publication number 20200411639
- Publication date Dec 31, 2020
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWALL INTERCONNECT METALLIZATION STRUCTURES FOR INTEGRATED CIRCU...
- Publication number 20200411433
- Publication date Dec 31, 2020
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20200411651
- Publication date Dec 31, 2020
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL LAYER WITH SUBSTANTIALLY PARALLEL SIDES
- Publication number 20200411315
- Publication date Dec 31, 2020
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...
- Publication number 20200411430
- Publication date Dec 31, 2020
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20200411365
- Publication date Dec 31, 2020
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METALLIZATION STRUCTURES FOR STACKED DEVICE CONNECTIVITY AND THEIR...
- Publication number 20200395386
- Publication date Dec 17, 2020
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Stacked source-drain-gate connection and process for forming such

Interconnect techniques for electrically connecting source/drain re...

Backside contacts for semiconductor devices

Isolation wall stressor structures to improve channel stress and th...

Epitaxial layer with substantially parallel sides

Leave-behind protective layer having secondary purpose

Stacked forksheet transistors

Sideways vias in isolation areas to contact interior layers in stac...

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process f...

Metallization structures for stacked device connectivity and their...

Gate-all-around integrated circuit structures having depopulated ch...

Sidewall interconnect metallization structures for integrated circu...

Gate-all-around integrated circuit structures having depopulated ch...

Forming an oxide volume within a fin

Interconnect techniques for electrically connecting source/drain re...

Vertically stacked transistor devices with isolation wall structure...

Stacked transistors having device strata with different channel widths

Stacked source-drain-gate connection and process for forming such

III-V source/drain in top NMOS transistors for low temperature stac...

Techniques for forming gate structures for transistors arranged in...

Vertical diode in stacked transistor architecture

Three dimensional integrated circuits with stacked transistors

Stacked trigate transistors with dielectric isolation between first...

Stacked transistors with different gate lengths in different device...

Stacked transistors with dielectric between channels of different d...

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Backside contacts for semiconductor devices

Transistors stacked on front-end p-type transistors

Patents Applicationslast 30 patents

BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

STACKED FORKSHEET TRANSISTORS

INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

FORMING AN OXIDE VOLUME WITHIN A FIN

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

INTERCONNECT TECHNIQUES FOR ELECTRICALLY CONNECTING SOURCE/DRAIN RE...

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS F...

CMOS ARCHITECTURE WITH THERMALLY STABLE SILICIDE GATE WORKFUNCTION...

BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

ISOLATION WALL STRESSOR STRUCTURES TO IMPROVE CHANNEL STRESS AND TH...

METALLIZATION STRUCTURES FOR STACKED DEVICE CONNECTIVITY AND THEIR...

LEAVE-BEHIND PROTECTIVE LAYER HAVING SECONDARY PURPOSE

VERTICALLY STACKED TRANSISTOR DEVICES WITH ISOLATION WALL STRUCTURE...

STACKED FORKSHEET TRANSISTORS

STACKED TRANSISTOR STRUCTURES WITH ASYMMETRICAL TERMINAL INTERCONNECTS

STACKED TRANSISTORS WITH SI PMOS AND HIGH MOBILITY THIN FILM TRANSI...

III-V SOURCE/DRAIN IN TOP NMOS TRANSISTORS FOR LOW TEMPERATURE STAC...

STACKED TRIGATE TRANSISTORS WITH DIELECTRIC ISOLATION AND PROCESS F...

MEMORY DEVICES WITH A LOGIC REGION BETWEEN MEMORY REGIONS

DEVICES WITH AIR GAPPING BETWEEN STACKED TRANSISTORS AND PROCESS FO...

SIDEWALL INTERCONNECT METALLIZATION STRUCTURES FOR INTEGRATED CIRCU...

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

EPITAXIAL LAYER WITH SUBSTANTIALLY PARALLEL SIDES

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...

FORMING AN OXIDE VOLUME WITHIN A FIN

METALLIZATION STRUCTURES FOR STACKED DEVICE CONNECTIVITY AND THEIR...