Ani Xavier

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus to reduce retimer latency and jitter
- Patent number 11,956,340
- Issue date Apr 9, 2024
- Texas Instruments Incorporated
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal transmission system for use with eye diagram monitor
- Patent number 11,855,816
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Rakesh Manjunath
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Charge pump with output current adjustment
- Patent number 11,722,142
- Issue date Aug 8, 2023
- Texas Instruments Incorporated
- Jagannathan Venkataraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Offset correction in high-speed serial link receivers
- Patent number 11,469,928
- Issue date Oct 11, 2022
- Texas Instruments Incorporated
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Calibration of skew between clock phases
- Patent number 11,416,021
- Issue date Aug 16, 2022
- Texas Instruments Incorporated
- Ani Xavier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial receiver equalization circuit
- Patent number 11,063,793
- Issue date Jul 13, 2021
- Texas Instruments Incorporated
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Top plate sampling circuit including input-dependent dual clock boo...
- Patent number 10,439,628
- Issue date Oct 8, 2019
- Texas Instruments Incorporated
- Ani Xavier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Negative capacitance circuits including temperature-compensation bi...
- Patent number 10,425,042
- Issue date Sep 24, 2019
- Texas Instruments Incorporated
- Ani Xavier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parasitic capacitance cancellation using dummy transistors
- Patent number 10,396,766
- Issue date Aug 27, 2019
- Texas Instruments Incorporated
- Basavaraj G. Gorguddi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pattern based estimation of errors in ADC
- Patent number 10,320,405
- Issue date Jun 11, 2019
- Texas Instruments Incorporated
- Srinivas Kumar Reddy Naru
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Top plate sampling circuit including input-dependent dual clock boo...
- Patent number 10,084,466
- Issue date Sep 25, 2018
- Texas Instruments Incorporated
- Ani Xavier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern based estimation of errors in ADC
- Patent number 9,941,893
- Issue date Apr 10, 2018
- Texas Instruments Incorporated
- Srinivas Kumar Reddy Naru
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER
- Publication number 20240259175
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER
- Publication number 20240113851
- Publication date Apr 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RETIMER WITH SLICER LEVEL ADJUSTMENT
- Publication number 20240030926
- Publication date Jan 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIGNAL TRANSMISSION SYSTEM FOR USE WITH EYE DIAGRAM MONITOR
- Publication number 20230054834
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Rakesh Manjunath
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CALIBRATION OF SKEW BETWEEN CLOCK PHASES
- Publication number 20220197330
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Ani XAVIER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Offset Correction in High-Speed Serial Link Receivers
- Publication number 20220182266
- Publication date Jun 9, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NEGATIVE CAPACITANCE CIRCUITS INCLUDING TEMPERATURE-COMPENSATION BI...
- Publication number 20190363679
- Publication date Nov 28, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Top Plate Sampling Circuit Including Input-Dependent Dual Clock Boo...
- Publication number 20190207617
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Ani XAVIER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGATIVE CAPACITANCE CIRCUITS INCLUDING TEMPERATURE-COMPENSATION BI...
- Publication number 20190207564
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Ani Xavier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARASITIC CAPACITANCE CANCELLATION USING DUMMY TRANSISTORS
- Publication number 20190199332
- Publication date Jun 27, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Basavaraj G. GORGUDDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN BASED ESTIMATION OF ERRORS IN ADC
- Publication number 20180191362
- Publication date Jul 5, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Srinivas Kumar Reddy Naru
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PATTERN BASED ESTIMATION OF ERRORS IN ADC
- Publication number 20170302287
- Publication date Oct 19, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Srinivas Kumar Reddy Naru
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Methods and apparatus to reduce retimer latency and jitter

Signal transmission system for use with eye diagram monitor

Charge pump with output current adjustment

Offset correction in high-speed serial link receivers

Calibration of skew between clock phases

Serial receiver equalization circuit

Top plate sampling circuit including input-dependent dual clock boo...

Negative capacitance circuits including temperature-compensation bi...

Parasitic capacitance cancellation using dummy transistors

Pattern based estimation of errors in ADC

Top plate sampling circuit including input-dependent dual clock boo...

Pattern based estimation of errors in ADC

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER

METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER

RETIMER WITH SLICER LEVEL ADJUSTMENT

SIGNAL TRANSMISSION SYSTEM FOR USE WITH EYE DIAGRAM MONITOR

CALIBRATION OF SKEW BETWEEN CLOCK PHASES

Offset Correction in High-Speed Serial Link Receivers

NEGATIVE CAPACITANCE CIRCUITS INCLUDING TEMPERATURE-COMPENSATION BI...

Top Plate Sampling Circuit Including Input-Dependent Dual Clock Boo...

NEGATIVE CAPACITANCE CIRCUITS INCLUDING TEMPERATURE-COMPENSATION BI...

PARASITIC CAPACITANCE CANCELLATION USING DUMMY TRANSISTORS

PATTERN BASED ESTIMATION OF ERRORS IN ADC

PATTERN BASED ESTIMATION OF ERRORS IN ADC