Animesh Datta

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout construction for addressing electromigration
- Patent number 11,508,725
- Issue date Nov 22, 2022
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 11,437,375
- Issue date Sep 6, 2022
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,600,785
- Issue date Mar 24, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,580,774
- Issue date Mar 3, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,074,609
- Issue date Sep 11, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Area efficient flip-flop with improved scan hold-margin
- Patent number 10,033,359
- Issue date Jul 24, 2018
- QUALCOMM Incorporated
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse-generator
- Patent number 9,979,394
- Issue date May 22, 2018
- QUALCOMM Incorporated
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,972,624
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low clock power data-gated flip-flop
- Patent number 9,966,953
- Issue date May 8, 2018
- QUALCOMM Incorporated
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous data-link throughput enhancement technique based on dat...
- Patent number 9,875,209
- Issue date Jan 23, 2018
- QUALCOMM Incorporated
- Lalan J. Mishra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,786,663
- Issue date Oct 10, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit techniques for efficient scan hold path design
- Patent number 9,678,154
- Issue date Jun 13, 2017
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop with reduced retention voltage
- Patent number 9,673,786
- Issue date Jun 6, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,659,936
- Issue date May 23, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compact design of scan latch
- Patent number 9,584,121
- Issue date Feb 28, 2017
- QUALCOMM Incorporated
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock-gating cell with low area, low power, and low setup time
- Patent number 9,577,635
- Issue date Feb 21, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Area-efficient metal-programmable pulse latch design
- Patent number 9,564,881
- Issue date Feb 7, 2017
- QUALCOMM Incorporated
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance standard cell with continuous oxide definition and...
- Patent number 9,318,476
- Issue date Apr 19, 2016
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital circuit design with semi-continuous diffusion standard cell
- Patent number 9,190,405
- Issue date Nov 17, 2015
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low overhead hold-violation fixing solution using metal-programable...
- Patent number 9,083,325
- Issue date Jul 14, 2015
- QUALCOMM Incorporated
- Animesh Datta
- G05 - CONTROLLING REGULATING
Information Patent Grant
Adaptive standard cell architecture and layout techniques for low a...
- Patent number 9,070,552
- Issue date Jun 30, 2015
- QUALCOMM Incorporated
- Jay Madhukar Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and layout techniques for flop tray area and power otimization
- Patent number 9,024,658
- Issue date May 5, 2015
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING
Information Patent Grant
High frequency synchronizer
- Patent number 9,020,084
- Issue date Apr 28, 2015
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Shared-diffusion standard cell architecture
- Patent number 8,836,040
- Issue date Sep 16, 2014
- QUALCOMM Incorporated
- Pratyush Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for characterizing and reducing proximity effe...
- Patent number 8,584,075
- Issue date Nov 12, 2013
- QUALCOMM Incorporated
- Animesh Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact and robust level shifter layout design
- Patent number 8,487,658
- Issue date Jul 16, 2013
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods using improved clock gating cells
- Patent number 8,030,982
- Issue date Oct 4, 2011
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20200168604
- Publication date May 28, 2020
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20200152630
- Publication date May 14, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20180342515
- Publication date Nov 29, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20180211957
- Publication date Jul 26, 2018
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW CLOCK POWER DATA-GATED FLIP-FLOP
- Publication number 20170353186
- Publication date Dec 7, 2017
- QUALCOMM Incorporated
- Qi YE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PULSE-GENERATOR
- Publication number 20170237434
- Publication date Aug 17, 2017
- QUALCOMM Incorporated
- Qi YE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20170221826
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AREA EFFICIENT FLIP-FLOP WITH IMPROVED SCAN HOLD-MARGIN
- Publication number 20170117884
- Publication date Apr 27, 2017
- QUALCOMM Incorporated
- Qi YE
- G01 - MEASURING TESTING
Information Patent Application
COMPACT DESIGN OF SCAN LATCH
- Publication number 20160365856
- Publication date Dec 15, 2016
- QUALCOMM Incorporated
- Qi YE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA-EFFICIENT METAL-PROGRAMMABLE PULSE LATCH DESIGN
- Publication number 20160344374
- Publication date Nov 24, 2016
- QUALCOMM Incorporated
- Qi YE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE LOW POWER AND HIGH PERFORMANCE LOGIC DESIGN AND PHYSICAL D...
- Publication number 20160217227
- Publication date Jul 28, 2016
- QUALCOMM Incorporated
- Peeyush Kumar PARKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME
- Publication number 20160211846
- Publication date Jul 21, 2016
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN
- Publication number 20160124043
- Publication date May 5, 2016
- Animesh Datta
- G01 - MEASURING TESTING
Information Patent Application
HIGH PERFORMANCE STANDARD CELL
- Publication number 20150249076
- Publication date Sep 3, 2015
- QUALCOMM Incorporated
- XIANGDONG CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIGITAL CIRCUIT DESIGN WITH SEMI-CONTINUOUS DIFFUSION STANDARD CELL
- Publication number 20150221639
- Publication date Aug 6, 2015
- QUALCOMM Incorporated
- Xiangdong CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20150054567
- Publication date Feb 26, 2015
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20150054568
- Publication date Feb 26, 2015
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL LOW OVERHEAD HOLD-VIOLATION FIXING SOLUTION USING METAL-PROGR...
- Publication number 20140368247
- Publication date Dec 18, 2014
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION
- Publication number 20140359385
- Publication date Dec 4, 2014
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING
Information Patent Application
SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DAT...
- Publication number 20140330994
- Publication date Nov 6, 2014
- QUALCOMM Incorporated
- Lalan J. Mishra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLIP-FLOP WITH REDUCED RETENTION VOLTAGE
- Publication number 20140306735
- Publication date Oct 16, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK-GATED SYNCHRONIZER
- Publication number 20140225655
- Publication date Aug 14, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH FREQUENCY SYNCHRONIZER
- Publication number 20140211893
- Publication date Jul 31, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SHARED-DIFFUSION STANDARD CELL ARCHITECTURE
- Publication number 20140124868
- Publication date May 8, 2014
- QUALCOMM Incorporated
- Pratyush Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact and Robust Level Shifter Layout Design
- Publication number 20130015882
- Publication date Jan 17, 2013
- QUALCOMM Incorporated
- Animesh Datta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Characterizing and Reducing Proximity Effe...
- Publication number 20120210284
- Publication date Aug 16, 2012
- QUALCOMM Incorporated
- Animesh Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods Using Improved Clock Gating Cells
- Publication number 20100109747
- Publication date May 6, 2010
- QUALCOMM Incorporated
- Animesh Datta
- H03 - BASIC ELECTRONIC CIRCUITRY

Animesh Datta

Person

Patents Grantslast 30 patents

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Area efficient flip-flop with improved scan hold-margin

Pulse-generator

Layout construction for addressing electromigration

Low clock power data-gated flip-flop

Synchronous data-link throughput enhancement technique based on dat...

Layout construction for addressing electromigration

Circuit techniques for efficient scan hold path design

Flip-flop with reduced retention voltage

Layout construction for addressing electromigration

Compact design of scan latch

Clock-gating cell with low area, low power, and low setup time

Area-efficient metal-programmable pulse latch design

High performance standard cell with continuous oxide definition and...

Digital circuit design with semi-continuous diffusion standard cell

Low overhead hold-violation fixing solution using metal-programable...

Adaptive standard cell architecture and layout techniques for low a...

Circuit and layout techniques for flop tray area and power otimization

High frequency synchronizer

Shared-diffusion standard cell architecture

Method and apparatus for characterizing and reducing proximity effe...

Compact and robust level shifter layout design

Systems and methods using improved clock gating cells

Patents Applicationslast 30 patents

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LOW CLOCK POWER DATA-GATED FLIP-FLOP

PULSE-GENERATOR

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

AREA EFFICIENT FLIP-FLOP WITH IMPROVED SCAN HOLD-MARGIN

COMPACT DESIGN OF SCAN LATCH

AREA-EFFICIENT METAL-PROGRAMMABLE PULSE LATCH DESIGN

ADAPTIVE LOW POWER AND HIGH PERFORMANCE LOGIC DESIGN AND PHYSICAL D...

CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME

CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN

HIGH PERFORMANCE STANDARD CELL

DIGITAL CIRCUIT DESIGN WITH SEMI-CONTINUOUS DIFFUSION STANDARD CELL

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

NOVEL LOW OVERHEAD HOLD-VIOLATION FIXING SOLUTION USING METAL-PROGR...

CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION

SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DAT...

FLIP-FLOP WITH REDUCED RETENTION VOLTAGE

CLOCK-GATED SYNCHRONIZER

HIGH FREQUENCY SYNCHRONIZER

SHARED-DIFFUSION STANDARD CELL ARCHITECTURE

Compact and Robust Level Shifter Layout Design

Method and Apparatus for Characterizing and Reducing Proximity Effe...

Systems and Methods Using Improved Clock Gating Cells