Aninda K. Roy

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for equalization in single-ended chip-to-chip...
- Patent number 7,433,396
- Issue date Oct 7, 2008
- Sun Microsystems, Inc.
- Aninda Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Fully stable clock domain synchronization technique for input/outpu...
- Patent number 7,376,855
- Issue date May 20, 2008
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simultaneous multi-band transmission on a printed circuit board
- Patent number 7,369,616
- Issue date May 6, 2008
- Sun Microsystems, Inc.
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic calibration of I/O power supply level
- Patent number 7,283,070
- Issue date Oct 16, 2007
- Sun Microsystems, Inc.
- Aninda K. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for receiver circuit tuning
- Patent number 7,263,628
- Issue date Aug 28, 2007
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance controlled transmitter with adaptive compensation for chi...
- Patent number 7,190,719
- Issue date Mar 13, 2007
- Sun Microsystems, Inc.
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receiver-side adaptive equalization in source-synchronous chip-to-c...
- Patent number 7,154,972
- Issue date Dec 26, 2006
- Sun Microsystems, Inc.
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technique for incorporating power information in register transfer...
- Patent number 7,146,303
- Issue date Dec 5, 2006
- Sun Microsystems, Inc.
- Aninda Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique to enlarge data eyes in wireline communication systems
- Patent number 7,110,461
- Issue date Sep 19, 2006
- Sun Microsystems, Inc.
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
I/O resonance cancellation circuit based on charge-pumped capacitors
- Patent number 7,062,662
- Issue date Jun 13, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating high speed parallel I/O interfaces based on counters
- Patent number 7,062,688
- Issue date Jun 13, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for quantifying I/O chip/package resonance
- Patent number 7,043,379
- Issue date May 9, 2006
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data transmission update technique in low power modes
- Patent number 7,043,683
- Issue date May 9, 2006
- Sun Microsystems, Inc.
- Brian W. Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Round-robin updating for high speed I/O parallel interfaces
- Patent number 7,017,086
- Issue date Mar 21, 2006
- Sun Microsystems, Inc.
- Aninda K. Roy
- G01 - MEASURING TESTING
Information Patent Grant
System, method and apparatus for improving sense amplifier performa...
- Patent number 6,975,144
- Issue date Dec 13, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G11 - INFORMATION STORAGE
Information Patent Grant
I/O interface anti-resonance passband shunting technique
- Patent number 6,909,203
- Issue date Jun 21, 2005
- Sun Microsystems, Inc.
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for I/O resonance compensation
- Patent number 6,842,351
- Issue date Jan 11, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Analog state recovery technique for DLL design
- Patent number 6,842,057
- Issue date Jan 11, 2005
- Sun Microsystems, Inc.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Design-for-test technique for a delay locked loop
- Patent number 6,815,986
- Issue date Nov 9, 2004
- Sun Microsystems, Inc.
- Aninda Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Source synchronous interface using variable digital data delay lines
- Patent number 6,791,360
- Issue date Sep 14, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unity gain interpolator for delay locked loops
- Patent number 6,788,123
- Issue date Sep 7, 2004
- n Microsystems, Inc.
- Aninda K. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
I/O power supply resonance compensation technique
- Patent number 6,781,355
- Issue date Aug 24, 2004
- Sun Microsystems, Inc.
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-resolution single-ended source-synchronous receiver
- Patent number 6,762,623
- Issue date Jul 13, 2004
- Sun Microsystems, Inc.
- Samudyatha Suryanarayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Self-biased driver amplifiers for high-speed signaling interfaces
- Patent number 6,756,824
- Issue date Jun 29, 2004
- Sun Microsystems, Inc.
- Aninda K. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay variability reduction method and apparatus
- Patent number 6,664,850
- Issue date Dec 16, 2003
- Sun Microsystems, Inc.
- Aninda Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Marginable clock-derived reference voltage method and apparatus
- Patent number 6,658,061
- Issue date Dec 2, 2003
- Sun Microsystems, Inc.
- Aninda Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic termination and clamping circuit
- Patent number 6,388,495
- Issue date May 14, 2002
- Sun Microsystems, Inc.
- Aninda Roy
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Methods and apparatus for equalization in single-ended chip-to-chip...
- Publication number 20040198267
- Publication date Oct 7, 2004
- Aninda Roy
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for receiver circuit tuning
- Publication number 20040177286
- Publication date Sep 9, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip-flop design with built-in voltage translation
- Publication number 20040169544
- Publication date Sep 2, 2004
- Aninda K. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Technique for incorporating power information in register transfer...
- Publication number 20040172232
- Publication date Sep 2, 2004
- Aninda Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simultaneous multi-band transmission on a printed circuit board
- Publication number 20040165670
- Publication date Aug 26, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for I/O resonance compensation
- Publication number 20040165406
- Publication date Aug 26, 2004
- Claude R. Gauthier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Nyquist pulse driver for data transmission
- Publication number 20040165671
- Publication date Aug 26, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System, method and apparatus for improving sense amplifier performa...
- Publication number 20040160243
- Publication date Aug 19, 2004
- SUN MICROSYSTEMS, INC.
- Claude R. Gauthier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data transmission update technique in low power modes
- Publication number 20040156396
- Publication date Aug 12, 2004
- Brian W. Amick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O interface anti-resonance passband shunting technique
- Publication number 20040150924
- Publication date Aug 5, 2004
- Claude Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-swing impedance controlled unity gain differential clock driver
- Publication number 20040130373
- Publication date Jul 8, 2004
- Aninda K. Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Impedance controlled transmitter with adaptive compensation for chi...
- Publication number 20040131128
- Publication date Jul 8, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Unity gain interpolator for delay locked loops
- Publication number 20040130371
- Publication date Jul 8, 2004
- Aninda K. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
I/O channel equalization based on low-frequency loss insertion
- Publication number 20040120419
- Publication date Jun 24, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Receiver-side adaptive equalization in source-synchronous chip-to-c...
- Publication number 20040120430
- Publication date Jun 24, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
I/O resonance cancellation circuit based on charge-pumped capacitors
- Publication number 20040123166
- Publication date Jun 24, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-RESOLUTION SINGLE-ENDED SOURCE-SYNCHRONOUS RECEIVER
- Publication number 20040113659
- Publication date Jun 17, 2004
- Samudyatha Suryanarayana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SELF-BIASED DRIVER AMPLIFIERS FOR HIGH-SPEED SIGNALING INTERFACES
- Publication number 20040090249
- Publication date May 13, 2004
- Aninda K. Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for quantifying I/O chip/package resonance
- Publication number 20040088624
- Publication date May 6, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
I/O Power supply resonance compensation technique
- Publication number 20040076025
- Publication date Apr 22, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Source synchronous interface using a dual loop delay locked loop an...
- Publication number 20040047441
- Publication date Mar 11, 2004
- Claude R. Gauthier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Source synchronous interface using variable digital data delay lines
- Publication number 20040046589
- Publication date Mar 11, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design-for-test technique for a delay locked loop
- Publication number 20040012420
- Publication date Jan 22, 2004
- Aninda Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Technique to enlarge data eyes in wireline communication systems
- Publication number 20040013203
- Publication date Jan 22, 2004
- Aninda K. Roy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Updating high speed parallel I/O interfaces based on counters
- Publication number 20040015751
- Publication date Jan 22, 2004
- Claude R. Gauthier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Round-robin updating for high speed i/o parallel interfaces
- Publication number 20030233608
- Publication date Dec 18, 2003
- Aninda K. Roy
- G01 - MEASURING TESTING

Aninda K. Roy

Person

Patents Grantslast 30 patents

Methods and apparatus for equalization in single-ended chip-to-chip...

Fully stable clock domain synchronization technique for input/outpu...

Simultaneous multi-band transmission on a printed circuit board

Dynamic calibration of I/O power supply level

Method and apparatus for receiver circuit tuning

Impedance controlled transmitter with adaptive compensation for chi...

Receiver-side adaptive equalization in source-synchronous chip-to-c...

Technique for incorporating power information in register transfer...

Technique to enlarge data eyes in wireline communication systems

I/O resonance cancellation circuit based on charge-pumped capacitors

Updating high speed parallel I/O interfaces based on counters

Method for quantifying I/O chip/package resonance

Data transmission update technique in low power modes

Round-robin updating for high speed I/O parallel interfaces

System, method and apparatus for improving sense amplifier performa...

I/O interface anti-resonance passband shunting technique

Method and apparatus for I/O resonance compensation

Analog state recovery technique for DLL design

Design-for-test technique for a delay locked loop

Source synchronous interface using variable digital data delay lines

Unity gain interpolator for delay locked loops

I/O power supply resonance compensation technique

High-resolution single-ended source-synchronous receiver

Self-biased driver amplifiers for high-speed signaling interfaces

Delay variability reduction method and apparatus

Marginable clock-derived reference voltage method and apparatus

Dynamic termination and clamping circuit

Patents Applicationslast 30 patents

Methods and apparatus for equalization in single-ended chip-to-chip...

Method and apparatus for receiver circuit tuning

Flip-flop design with built-in voltage translation

Technique for incorporating power information in register transfer...

Simultaneous multi-band transmission on a printed circuit board

Method and apparatus for I/O resonance compensation

Nyquist pulse driver for data transmission

System, method and apparatus for improving sense amplifier performa...

Data transmission update technique in low power modes

I/O interface anti-resonance passband shunting technique

Low-swing impedance controlled unity gain differential clock driver

Impedance controlled transmitter with adaptive compensation for chi...

Unity gain interpolator for delay locked loops

I/O channel equalization based on low-frequency loss insertion

Receiver-side adaptive equalization in source-synchronous chip-to-c...

I/O resonance cancellation circuit based on charge-pumped capacitors

HIGH-RESOLUTION SINGLE-ENDED SOURCE-SYNCHRONOUS RECEIVER

SELF-BIASED DRIVER AMPLIFIERS FOR HIGH-SPEED SIGNALING INTERFACES

Method for quantifying I/O chip/package resonance

I/O Power supply resonance compensation technique

Source synchronous interface using a dual loop delay locked loop an...

Source synchronous interface using variable digital data delay lines

Design-for-test technique for a delay locked loop

Technique to enlarge data eyes in wireline communication systems

Updating high speed parallel I/O interfaces based on counters

Round-robin updating for high speed i/o parallel interfaces