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Ankush Sood
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San Jose, CA, US
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last 30 patents
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Patent Grant
Clock topology planning for reduced power consumption
Patent number
9,411,912
Issue date
Aug 9, 2016
Cadence Design Systems, Inc.
Ankush Sood
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Methods, systems, and apparatus for clock topology planning with re...
Patent number
9,280,614
Issue date
Mar 8, 2016
Cadence Design Systems, Inc.
Ankush Sood
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Methods for construction and optimization of a clock tree plan for...
Patent number
9,135,375
Issue date
Sep 15, 2015
Cadence Design Systems, Inc.
Ankush Sood
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Graphical user interface for physically aware clock tree planning
Patent number
8,826,211
Issue date
Sep 2, 2014
Cadence Design Systems, Inc.
Ankush Sood
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Physically aware logic synthesis of integrated circuit designs
Patent number
8,782,591
Issue date
Jul 15, 2014
Cadence Design Systems, Inc.
Tsuwei Ku
G06 - COMPUTING CALCULATING COUNTING