Anshuman Chandra

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automatically generated schematics and visualization
- Patent number 10,621,298
- Issue date Apr 14, 2020
- Synopsys, Inc.
- Anshuman Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of undesirable distribution of unknown values in testing o...
- Patent number 10,067,187
- Issue date Sep 4, 2018
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,417,287
- Issue date Aug 16, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical testing architecture using core circuit with pseudo-in...
- Patent number 9,239,897
- Issue date Jan 19, 2016
- Synopsys, Inc.
- Subramanian B. Chebiyam
- G01 - MEASURING TESTING
Information Patent Grant
Test architecture including cyclical cache chains, selective bypass...
- Patent number 8,479,067
- Issue date Jul 2, 2013
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Implementing hierarchical design-for-test logic for modular circuit...
- Patent number 8,065,651
- Issue date Nov 22, 2011
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATICALLY GENERATED SCHEMATICS AND VISUALIZATION
- Publication number 20170116364
- Publication date Apr 27, 2017
- Synopsys, Inc.
- Anshuman Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20160341795
- Publication date Nov 24, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Handling of Undesirable Distribution of Unknown Values in Testing o...
- Publication number 20150025819
- Publication date Jan 22, 2015
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20140317463
- Publication date Oct 23, 2014
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical Testing Architecture Using Core Circuit with Pseudo-In...
- Publication number 20140304672
- Publication date Oct 9, 2014
- Subramanian B. Chebiyam
- G01 - MEASURING TESTING
Information Patent Application
Test Architecture Including Cyclical Cache Chains, Selective Bypass...
- Publication number 20110258498
- Publication date Oct 20, 2011
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...
- Publication number 20100192030
- Publication date Jul 29, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING

Anshuman Chandra

Person

Patents Grantslast 30 patents

Automatically generated schematics and visualization

Handling of undesirable distribution of unknown values in testing o...

Scheme for masking output of scan chains in test circuit

Hierarchical testing architecture using core circuit with pseudo-in...

Test architecture including cyclical cache chains, selective bypass...

Implementing hierarchical design-for-test logic for modular circuit...

Patents Applicationslast 30 patents

AUTOMATICALLY GENERATED SCHEMATICS AND VISUALIZATION

Scheme for Masking Output of Scan Chains in Test Circuit

Handling of Undesirable Distribution of Unknown Values in Testing o...

Scheme for Masking Output of Scan Chains in Test Circuit

Hierarchical Testing Architecture Using Core Circuit with Pseudo-In...

Test Architecture Including Cyclical Cache Chains, Selective Bypass...

METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...