Anthony D. Polson

Person

Jericho Center, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-going reliability monitoring of integrated circuit chips in the...
- Patent number 9,310,426
- Issue date Apr 12, 2016
- GLOBALFOUNDRIES Inc.
- Theodoros E. Anemikos
- G11 - INFORMATION STORAGE
Information Patent Grant
Detecting chip alterations with light emission
- Patent number 9,075,106
- Issue date Jul 7, 2015
- International Business Machines Corporation
- Kerry Bernstein
- G01 - MEASURING TESTING
Information Patent Grant
Characterization of long range variability
- Patent number 8,336,008
- Issue date Dec 18, 2012
- International Business Machines Corporation
- James A. Culp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for evaluating timing in an integrated circuit
- Patent number 7,962,874
- Issue date Jun 14, 2011
- International Business Machines Corporation
- Eric A. Foreman
- G01 - MEASURING TESTING
Information Patent Grant
Method of laying out integrated circuit design based on known polys...
- Patent number 7,890,906
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to optimize semiconductor power by integration of...
- Patent number 7,877,714
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Theodoros E. Anemikos
- G01 - MEASURING TESTING
Information Patent Grant
Slack sensitivity to parameter variation based timing analysis
- Patent number 7,870,525
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of generating wiring routes with matching delay in the prese...
- Patent number 7,865,861
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with uniform polysilicon perimeter density, meth...
- Patent number 7,849,433
- Issue date Dec 7, 2010
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,840,864
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,840,863
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating wiring routes with matching delay in the prese...
- Patent number 7,823,115
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing power usage of an integrated circuit design by...
- Patent number 7,810,054
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Theodoros E. Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC chip design modeling using perimeter density to electrical chara...
- Patent number 7,805,693
- Issue date Sep 28, 2010
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth low-latency semaphore mapped protocol (SMP) for mult...
- Patent number 7,765,351
- Issue date Jul 27, 2010
- International Business Machines Corporation
- Pascal A. Nsame
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slack sensitivity to parameter variation based timing analysis
- Patent number 7,716,616
- Issue date May 11, 2010
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,698,611
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Gary Grise
- G01 - MEASURING TESTING
Information Patent Grant
System and method of analyzing timing effects of spatial distributi...
- Patent number 7,680,626
- Issue date Mar 16, 2010
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-skew tuning apparatus and method
- Patent number 7,521,973
- Issue date Apr 21, 2009
- International Business Machines Corporation
- Theodoros E Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for chip-level testing of wire delay independe...
- Patent number 7,489,204
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Peter A. Habitz
- G01 - MEASURING TESTING
Information Patent Grant
Design structure for monitoring cross chip delay variation on a sem...
- Patent number 7,487,487
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Anthony D. Polson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for evaluating timing in an integrated circuit
- Patent number 7,444,608
- Issue date Oct 28, 2008
- International Business Machines Corporation
- Eric A. Foreman
- G01 - MEASURING TESTING
Information Patent Grant
Method of generating wiring routes with matching delay in the prese...
- Patent number 7,418,689
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slack sensitivity to parameter variation based timing analysis
- Patent number 7,401,307
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing shapes correction of a multi-cell...
- Patent number 7,302,673
- Issue date Nov 27, 2007
- International Business Machines Corporation
- Peter Anton Habitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,290,191
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
System and method of analyzing timing effects of spatial distributi...
- Patent number 7,280,939
- Issue date Oct 9, 2007
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for evaluating timing in an integrated circuit
- Patent number 7,089,143
- Issue date Aug 8, 2006
- International Business Machines Corporation
- Eric A. Foreman
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ON-GOING RELIABILITY MONITORING OF INTEGRATED CIRCUIT CHIPS IN THE...
- Publication number 20140088947
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Theodoros E. Anemikos
- G01 - MEASURING TESTING
Information Patent Application
Characterization of Long Range Variability
- Publication number 20110078641
- Publication date Mar 31, 2011
- International Business Machines Corporation
- James A. Culp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detecting Chip Alterations with Light Emission
- Publication number 20110026806
- Publication date Feb 3, 2011
- International Business Machines Corporation
- Kerry Bernstein
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20100088561
- Publication date Apr 8, 2010
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20100088562
- Publication date Apr 8, 2010
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYS...
- Publication number 20090282380
- Publication date Nov 12, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METH...
- Publication number 20090278222
- Publication date Nov 12, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CU...
- Publication number 20090228843
- Publication date Sep 10, 2009
- International Business Machines Corporation
- Theodoros E. Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF...
- Publication number 20090217221
- Publication date Aug 27, 2009
- International Business Machines Corporation
- Theodoros E. ANEMIKOS
- G01 - MEASURING TESTING
Information Patent Application
IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARA...
- Publication number 20090210834
- Publication date Aug 20, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Structure for an Integrated Circuit Having State-Saving Inpu...
- Publication number 20090115447
- Publication date May 7, 2009
- International Business Machines Corporation
- Theodoros E. Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT
- Publication number 20080313590
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Eric A. FOREMAN
- G01 - MEASURING TESTING
Information Patent Application
High Bandwidth Low-Latency Semaphore Mapped Protocol (SMP) For Mult...
- Publication number 20080229006
- Publication date Sep 18, 2008
- Pascal A. Nsame
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
- Publication number 20080216036
- Publication date Sep 4, 2008
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Generating Wiring Routes with Matching Delay in the Prese...
- Publication number 20080201683
- Publication date Aug 21, 2008
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Generating Wiring Routes with Matching Delay in the Prese...
- Publication number 20080195993
- Publication date Aug 14, 2008
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Having State-Saving Input-Output Circuitry and a...
- Publication number 20080129330
- Publication date Jun 5, 2008
- International Business Machines Corporation
- Theodoros Anemikos
- G01 - MEASURING TESTING
Information Patent Application
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
- Publication number 20080052656
- Publication date Feb 28, 2008
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20070283201
- Publication date Dec 6, 2007
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTI...
- Publication number 20070220345
- Publication date Sep 20, 2007
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION
- Publication number 20070061771
- Publication date Mar 15, 2007
- International Business Machines Corporation
- Peter Anton Habitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD AND STRUCTURE FOR CHIP-LEVEL TESTING OF WIRE DELAY INDEPENDE...
- Publication number 20070001682
- Publication date Jan 4, 2007
- International Business Machines Corporation
- Peter A. Habitz
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESE...
- Publication number 20060248488
- Publication date Nov 2, 2006
- International Business Machines Corporation
- Peter A. Habitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGATED CIRCUIT
- Publication number 20060195807
- Publication date Aug 31, 2006
- International Business Machines Corporation
- Eric A. Foreman
- G01 - MEASURING TESTING
Information Patent Application
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
- Publication number 20060101361
- Publication date May 11, 2006
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20060041802
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT
- Publication number 20050246116
- Publication date Nov 3, 2005
- International Business Machines Corporation
- Eric A. Foreman
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTI...
- Publication number 20050246117
- Publication date Nov 3, 2005
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING

Anthony D. Polson

Person

Patents Grantslast 30 patents

On-going reliability monitoring of integrated circuit chips in the...

Detecting chip alterations with light emission

Characterization of long range variability

Method and system for evaluating timing in an integrated circuit

Method of laying out integrated circuit design based on known polys...

System and method to optimize semiconductor power by integration of...

Slack sensitivity to parameter variation based timing analysis

Method of generating wiring routes with matching delay in the prese...

Integrated circuit with uniform polysilicon perimeter density, meth...

Functional frequency testing of integrated circuits

Functional frequency testing of integrated circuits

Method of generating wiring routes with matching delay in the prese...

Method of optimizing power usage of an integrated circuit design by...

IC chip design modeling using perimeter density to electrical chara...

High bandwidth low-latency semaphore mapped protocol (SMP) for mult...

Slack sensitivity to parameter variation based timing analysis

Functional frequency testing of integrated circuits

System and method of analyzing timing effects of spatial distributi...

Clock-skew tuning apparatus and method

Method and structure for chip-level testing of wire delay independe...

Design structure for monitoring cross chip delay variation on a sem...

Method and system for evaluating timing in an integrated circuit

Method of generating wiring routes with matching delay in the prese...

Slack sensitivity to parameter variation based timing analysis

Method and system for performing shapes correction of a multi-cell...

Functional frequency testing of integrated circuits

System and method of analyzing timing effects of spatial distributi...

Method and system for evaluating timing in an integrated circuit

Patents Applicationslast 30 patents

ON-GOING RELIABILITY MONITORING OF INTEGRATED CIRCUIT CHIPS IN THE...

Characterization of Long Range Variability

Detecting Chip Alterations with Light Emission

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYS...

INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METH...

METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CU...

SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF...

IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARA...

Design Structure for an Integrated Circuit Having State-Saving Inpu...

METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT

High Bandwidth Low-Latency Semaphore Mapped Protocol (SMP) For Mult...

SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS

Method of Generating Wiring Routes with Matching Delay in the Prese...

Method of Generating Wiring Routes with Matching Delay in the Prese...

Integrated Circuit Having State-Saving Input-Output Circuitry and a...

SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTI...

METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION

METHOD AND STRUCTURE FOR CHIP-LEVEL TESTING OF WIRE DELAY INDEPENDE...

METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESE...

METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGATED CIRCUIT

SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT

SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTI...