Anthony D. Weathers

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Encoding system data in parity symbols
- Patent number 12,182,415
- Issue date Dec 31, 2024
- Microsoft Technology Licensing, LLC
- Majid Anaraki Nemati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symbol rotation of cache line codewords for increased reliability w...
- Patent number 12,181,971
- Issue date Dec 31, 2024
- Microsoft Technology Licensing, LLC
- Majid Anaraki Nemati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 11,815,996
- Issue date Nov 14, 2023
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level tracking and optimization
- Patent number 11,621,043
- Issue date Apr 4, 2023
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating optimal read levels
- Patent number 11,488,673
- Issue date Nov 1, 2022
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for encoding and decoding data
- Patent number 11,403,031
- Issue date Aug 2, 2022
- Microsoft Technology Licensing, LLC
- Anthony D. Weathers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 11,327,837
- Issue date May 10, 2022
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level tracking and optimization
- Patent number 11,101,006
- Issue date Aug 24, 2021
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 10,884,854
- Issue date Jan 5, 2021
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level tracking and optimization
- Patent number 10,748,628
- Issue date Aug 18, 2020
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating optimal read levels
- Patent number 10,566,061
- Issue date Feb 18, 2020
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft information module
- Patent number 10,510,405
- Issue date Dec 17, 2019
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for scanning for erased flash memory pages
- Patent number 10,387,246
- Issue date Aug 20, 2019
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level tracking and optimization
- Patent number 10,236,070
- Issue date Mar 19, 2019
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level grouping algorithms for increased flash performance
- Patent number 9,905,302
- Issue date Feb 27, 2018
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft information module
- Patent number 9,881,670
- Issue date Jan 30, 2018
- HGST Technologies Santa Ana, Inc.
- Anthony Dwayne Weathers
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read level grouping for increased flash performance
- Patent number 9,720,754
- Issue date Aug 1, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Read level grouping algorithms for increased flash performance
- Patent number 9,583,202
- Issue date Feb 28, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibrating optimal read levels
- Patent number 9,576,671
- Issue date Feb 21, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Word-line inter-cell interference detector in flash system
- Patent number 9,343,170
- Issue date May 17, 2016
- HGST Technologies Santa Ana, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Read level adjustment using soft information
- Patent number 9,135,106
- Issue date Sep 15, 2015
- HGST Technologies Santa Ana, Inc.
- Anthony D. Weathers
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft information module
- Patent number 9,136,011
- Issue date Sep 15, 2015
- HGST Technologies Santa Ana, Inc.
- Anthony D. Weathers
- G11 - INFORMATION STORAGE
Information Patent Grant
Inter-cell interference algorithms for soft decoding of LDPC codes
- Patent number 9,117,529
- Issue date Aug 25, 2015
- HGST Technologies Santa Ana, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for encoding LBA information into the parity o...
- Patent number 8,880,976
- Issue date Nov 4, 2014
- STMicroelectronics, Inc.
- Anthony Weathers
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for multi-mode operation of a flash memory device
- Patent number 8,656,256
- Issue date Feb 18, 2014
- Stec, Inc.
- Anthony D. Weathers
- G11 - INFORMATION STORAGE
Information Patent Grant
Trellis-coded modulation in a multi-level cell flash memory device
- Patent number 8,656,263
- Issue date Feb 18, 2014
- Stec, Inc.
- Xinde Hu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for determining data dependent noise calculation...
- Patent number 8,605,501
- Issue date Dec 10, 2013
- Stec, Inc.
- Xinde Hu
- G11 - INFORMATION STORAGE
Information Patent Grant
Word-line inter-cell interference detector in flash system
- Patent number 8,493,791
- Issue date Jul 23, 2013
- Stec, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimal programming levels for LDPC
- Patent number 8,484,519
- Issue date Jul 9, 2013
- Stec, Inc.
- Anthony D. Weathers
- G11 - INFORMATION STORAGE
Information Patent Grant
Interlaced iterative system design for 1K-byte block with 512-byte...
- Patent number 8,255,768
- Issue date Aug 28, 2012
- STMicroelectronics, Inc.
- Xinde Hu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYMBOL ROTATION OF CACHE LINE CODEWORDS FOR INCREASED RELIABILITY W...
- Publication number 20240419550
- Publication date Dec 19, 2024
- Microsoft Technology Licensing, LLC
- Majid Anaraki NEMATI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING SYSTEM DATA IN PARITY SYMBOLS
- Publication number 20230359367
- Publication date Nov 9, 2023
- Microsoft Technology Licensing, LLC
- Majid Anaraki NEMATI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CODES TO DETECT INSERTION AND DELETION ERRORS IN A DENSE STORAGE ME...
- Publication number 20220284304
- Publication date Sep 8, 2022
- Microsoft Technology Licensing, LLC
- Majid Anaraki NEMATI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Identifying Erased Memory Areas
- Publication number 20220214941
- Publication date Jul 7, 2022
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read Level Tracking and Optimization
- Publication number 20210319837
- Publication date Oct 14, 2021
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ENCODING AND DECODING DATA
- Publication number 20210141558
- Publication date May 13, 2021
- Microsoft Technology Licensing, LLC
- Anthony D. WEATHERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS
- Publication number 20210103496
- Publication date Apr 8, 2021
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read Level Tracking and Optimization
- Publication number 20200335173
- Publication date Oct 22, 2020
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibrating Optimal Read Levels
- Publication number 20200160920
- Publication date May 21, 2020
- Western Digital Technologies, Inc.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS
- Publication number 20190324853
- Publication date Oct 24, 2019
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL TRACKING AND OPTIMIZATION
- Publication number 20190214101
- Publication date Jul 11, 2019
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SCANNING FOR ERASED FLASH MEMORY PAGES
- Publication number 20180373591
- Publication date Dec 27, 2018
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL TRACKING AND OPTIMIZATION
- Publication number 20180374550
- Publication date Dec 27, 2018
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFT INFORMATION MODULE
- Publication number 20180151222
- Publication date May 31, 2018
- HGST Technologies Santa Ana, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALIBRATING OPTIMAL READ LEVELS
- Publication number 20170229186
- Publication date Aug 10, 2017
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL GROUPING FOR INCREASED FLASH PERFORMANCE
- Publication number 20160147582
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE
- Publication number 20160148701
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
CALIBRATING OPTIMAL READ LEVELS
- Publication number 20160148702
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFT INFORMATION MODULE
- Publication number 20160005460
- Publication date Jan 7, 2016
- HGST Technologies Santa Ana, Inc.
- Anthony Dwayne WEATHERS
- G11 - INFORMATION STORAGE
Information Patent Application
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
- Publication number 20150371714
- Publication date Dec 24, 2015
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
- Publication number 20150364202
- Publication date Dec 17, 2015
- HGST Technologies Santa Ana, Inc.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
READ LEVEL ADJUSTMENT USING SOFT INFORMATION
- Publication number 20130318422
- Publication date Nov 28, 2013
- STEC, Inc.
- Anthony D. Weathers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFT INFORMATION MODULE
- Publication number 20130290612
- Publication date Oct 31, 2013
- STEC, Inc.
- Anthony D. Weathers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
- Publication number 20130163327
- Publication date Jun 27, 2013
- STEC, Inc.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
- Publication number 20130163328
- Publication date Jun 27, 2013
- STEC, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Application
OPTIMAL PROGRAMMING LEVELS FOR LDPC
- Publication number 20130047044
- Publication date Feb 21, 2013
- STEC, Inc.
- Anthony D. Weathers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR INDICATOR FROM ECC DECODER
- Publication number 20130047045
- Publication date Feb 21, 2013
- STEC, Inc.
- Xinde Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE
- Publication number 20120240012
- Publication date Sep 20, 2012
- STEC, Inc.
- Anthony D. WEATHERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRELLIS-CODED MODULATION IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE
- Publication number 20120240006
- Publication date Sep 20, 2012
- STEC, Inc.
- Xinde Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LDPC DECODING FOR SOLID STATE STORAGE DEVICES
- Publication number 20120240007
- Publication date Sep 20, 2012
- STEC, Inc.
- Richard D. BARNDT
- H03 - BASIC ELECTRONIC CIRCUITRY

Anthony D. Weathers

Person

Patents Grantslast 30 patents

Encoding system data in parity symbols

Symbol rotation of cache line codewords for increased reliability w...

Method and system for identifying erased memory areas

Read level tracking and optimization

Calibrating optimal read levels

Systems and methods for encoding and decoding data

Method and system for identifying erased memory areas

Read level tracking and optimization

Method and system for identifying erased memory areas

Read level tracking and optimization

Calibrating optimal read levels

Soft information module

Method and system for scanning for erased flash memory pages

Read level tracking and optimization

Read level grouping algorithms for increased flash performance

Soft information module

Read level grouping for increased flash performance

Read level grouping algorithms for increased flash performance

Calibrating optimal read levels

Word-line inter-cell interference detector in flash system

Read level adjustment using soft information

Soft information module

Inter-cell interference algorithms for soft decoding of LDPC codes

Method and apparatus for encoding LBA information into the parity o...

Apparatus and method for multi-mode operation of a flash memory device

Trellis-coded modulation in a multi-level cell flash memory device

System and method for determining data dependent noise calculation...

Word-line inter-cell interference detector in flash system

Optimal programming levels for LDPC

Interlaced iterative system design for 1K-byte block with 512-byte...

Patents Applicationslast 30 patents

SYMBOL ROTATION OF CACHE LINE CODEWORDS FOR INCREASED RELIABILITY W...

ENCODING SYSTEM DATA IN PARITY SYMBOLS

CODES TO DETECT INSERTION AND DELETION ERRORS IN A DENSE STORAGE ME...

Method and System for Identifying Erased Memory Areas

Read Level Tracking and Optimization

SYSTEMS AND METHODS FOR ENCODING AND DECODING DATA

METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS

Read Level Tracking and Optimization

Calibrating Optimal Read Levels

METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS

READ LEVEL TRACKING AND OPTIMIZATION

METHOD AND SYSTEM FOR SCANNING FOR ERASED FLASH MEMORY PAGES

READ LEVEL TRACKING AND OPTIMIZATION

SOFT INFORMATION MODULE

CALIBRATING OPTIMAL READ LEVELS

READ LEVEL GROUPING FOR INCREASED FLASH PERFORMANCE

READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE

CALIBRATING OPTIMAL READ LEVELS

SOFT INFORMATION MODULE

WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM

INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES

READ LEVEL ADJUSTMENT USING SOFT INFORMATION

SOFT INFORMATION MODULE

WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM

INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES

OPTIMAL PROGRAMMING LEVELS FOR LDPC

ERROR INDICATOR FROM ECC DECODER

APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE

TRELLIS-CODED MODULATION IN A MULTI-LEVEL CELL FLASH MEMORY DEVICE

LDPC DECODING FOR SOLID STATE STORAGE DEVICES