Anthony M. Petro

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for a 1 of N signal
- Patent number 6,911,846
- Issue date Jun 28, 2005
- Intrinsity, Inc.
- James S. Blomgren
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a N-NARY logic circuit using capacitance i...
- Patent number 6,571,378
- Issue date May 27, 2003
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for N-nary incrementor
- Patent number 6,347,327
- Issue date Feb 12, 2002
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic 3-level partial result merge adder
- Patent number 6,334,136
- Issue date Dec 25, 2001
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling partial register accesses
- Patent number 6,334,183
- Issue date Dec 25, 2001
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a 1 of 4 shifter
- Patent number 6,324,239
- Issue date Nov 27, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamic partitionable saturating adder/sub...
- Patent number 6,301,600
- Issue date Oct 9, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for saturation in an N-NARY adder/subtractor
- Patent number 6,301,597
- Issue date Oct 9, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating clock signals
- Patent number 6,288,589
- Issue date Sep 11, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
1-of-4 multiplier
- Patent number 6,275,841
- Issue date Aug 14, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for interruption of carry propagation on parti...
- Patent number 6,272,514
- Issue date Aug 7, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for logic synchronization
- Patent number 6,268,746
- Issue date Jul 31, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for 3-stage 32-bit adder/subtractor
- Patent number 6,269,387
- Issue date Jul 31, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-NARY logic circuit
- Patent number 6,252,425
- Issue date Jun 26, 2001
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus that allows the logic state of a logic gate to...
- Patent number 6,233,707
- Issue date May 15, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-NARY HPG gate
- Patent number 6,223,199
- Issue date Apr 24, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-nary Sum/HPG gate
- Patent number 6,219,687
- Issue date Apr 17, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-NARY sum/HPG adder/subtractor gate
- Patent number 6,219,686
- Issue date Apr 17, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-nary adder gate
- Patent number 6,216,146
- Issue date Apr 10, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-nary magnitude comparator
- Patent number 6,216,147
- Issue date Apr 10, 2001
- Intrinsity, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-nary equality comparator
- Patent number 6,154,120
- Issue date Nov 28, 2000
- Evsx, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-nary logic circuit using capacitance i...
- Patent number 6,124,735
- Issue date Sep 26, 2000
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for logic synchronization
- Patent number 6,118,304
- Issue date Sep 12, 2000
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a logic circuit with constant power consum...
- Patent number 6,107,835
- Issue date Aug 22, 2000
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-nary logic circuit using 1 of N signals
- Patent number 6,069,497
- Issue date May 30, 2000
- Evsx, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-nary logic circuit using 1 of 4 signals
- Patent number 6,066,965
- Issue date May 23, 2000
- Evsx, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for efficient loop control in a superscalar mi...
- Patent number 6,032,252
- Issue date Feb 29, 2000
- Advanced Micro Devices, Inc.
- Anthony M. Petro
- G06 - COMPUTING CALCULATING COUNTING

Anthony M. Petro

Person

Patents Grantslast 30 patents

Method and apparatus for a 1 of N signal

Method and apparatus for a N-NARY logic circuit using capacitance i...

Method and apparatus for N-nary incrementor

Dynamic 3-level partial result merge adder

Method and apparatus for handling partial register accesses

Method and apparatus for a 1 of 4 shifter

Method and apparatus for dynamic partitionable saturating adder/sub...

Method and apparatus for saturation in an N-NARY adder/subtractor

Method and apparatus for generating clock signals

1-of-4 multiplier

Method and apparatus for interruption of carry propagation on parti...

Method and apparatus for logic synchronization

Method and apparatus for 3-stage 32-bit adder/subtractor

Method and apparatus for an N-NARY logic circuit

Method and apparatus that allows the logic state of a logic gate to...

Method and apparatus for an N-NARY HPG gate

Method and apparatus for an N-nary Sum/HPG gate

Method and apparatus for an N-NARY sum/HPG adder/subtractor gate

Method and apparatus for an N-nary adder gate

Method and apparatus for an N-nary magnitude comparator

Method and apparatus for an N-nary equality comparator

Method and apparatus for a N-nary logic circuit using capacitance i...

Method and apparatus for logic synchronization

Method and apparatus for a logic circuit with constant power consum...

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Apparatus and method for efficient loop control in a superscalar mi...