Antonino Pollio

Person

Vico Equense ( NA), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Data separation for garbage collection
- Patent number 12,141,059
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Idle mode temperature control for memory systems
- Patent number 12,039,189
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Francesco Basso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split cache for address mapping data
- Patent number 12,007,897
- Issue date Jun 11, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic updates to logical-to-physical address translation table bi...
- Patent number 11,928,063
- Issue date Mar 12, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancement for activation and deactivation of memory address regions
- Patent number 11,886,341
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for page line filler data
- Patent number 11,768,627
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization techniques for memory devices
- Patent number 11,657,878
- Issue date May 23, 2023
- Micron Technology, Inc.
- Antonino Pollio
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for page line filler data
- Patent number 11,556,275
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data separation for garbage collection
- Patent number 11,513,952
- Issue date Nov 29, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split cache for address mapping data
- Patent number 11,429,528
- Issue date Aug 30, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancement for activation and deactivation of memory address regions
- Patent number 11,379,367
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization techniques for memory devices
- Patent number 11,238,940
- Issue date Feb 1, 2022
- Micron Technology, Inc.
- Antonino Pollio
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for executing a plurality of queued tasks i...
- Patent number 11,023,167
- Issue date Jun 1, 2021
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program progress monitoring in a memory array
- Patent number 10,614,899
- Issue date Apr 7, 2020
- Micron Technology, Inc.
- Giuseppe Cariello
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for executing a plurality of queued tasks i...
- Patent number 10,108,372
- Issue date Oct 23, 2018
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller to manage NAND memories
- Patent number 9,971,536
- Issue date May 15, 2018
- Micron Technology, Inc.
- Federico Tiziani
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to manage NAND memories
- Patent number 9,569,129
- Issue date Feb 14, 2017
- Micron Technology, Inc.
- Federico Tiziani
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to manage NAND memories
- Patent number 9,213,603
- Issue date Dec 15, 2015
- Micron Technology, Inc.
- Federico Tiziani
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Wear leveling for erasable memories
- Patent number 9,189,390
- Issue date Nov 17, 2015
- Micron Technology, Inc.
- Massimo Iaculo
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to execute error correcting code algorithms and manage N...
- Patent number 8,806,293
- Issue date Aug 12, 2014
- Micron Technology, Inc.
- Federico Tiziani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wear leveling for erasable memories
- Patent number 8,694,718
- Issue date Apr 8, 2014
- Micron Technology, Inc.
- Massimo Iaculo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS
- Publication number 20240419353
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Francesco Basso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIRMWARE VERIFICATION USING PARITY INFORMATION
- Publication number 20240394371
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Flavio Pace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITING USER DATA INTO STORAGE MEMORY
- Publication number 20240185926
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...
- Publication number 20240168889
- Publication date May 23, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS
- Publication number 20240069784
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Francesco Basso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...
- Publication number 20240061787
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PAGE LINE FILLER DATA
- Publication number 20230244414
- Publication date Aug 3, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA SEPARATION FOR GARBAGE COLLECTION
- Publication number 20230161696
- Publication date May 25, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLIT CACHE FOR ADDRESS MAPPING DATA
- Publication number 20230015332
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SETTING SWITCHING FOR SINGLE-LEVEL CELLS
- Publication number 20220406388
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS
- Publication number 20220405205
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PAGE LINE FILLER DATA
- Publication number 20220374163
- Publication date Nov 24, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZATION TECHNIQUES FOR MEMORY DEVICES
- Publication number 20220223211
- Publication date Jul 14, 2022
- Micron Technology, Inc.
- Antonino Pollio
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS
- Publication number 20220156185
- Publication date May 19, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLIT CACHE FOR ADDRESS MAPPING DATA
- Publication number 20220156196
- Publication date May 19, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA SEPARATION FOR GARBAGE COLLECTION
- Publication number 20220004493
- Publication date Jan 6, 2022
- Micron Technology, Inc.
- Nicola Colella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM PROGESS MONITORING IN A MEMORY ARRAY
- Publication number 20200005880
- Publication date Jan 2, 2020
- Giuseppe Cariello
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES FOR EXECUTING A PLURALITY OF QUEUED TASKS I...
- Publication number 20190018618
- Publication date Jan 17, 2019
- Micron Technology, Inc.
- GIUSEPPE D'ELISEO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER TO MANAGE NAND MEMORIES
- Publication number 20170160973
- Publication date Jun 8, 2017
- Micron Technology, Inc.
- Federico Tiziani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER TO MANAGE NAND MEMORIES
- Publication number 20160098223
- Publication date Apr 7, 2016
- Federico Tiziani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUSES FOR EXECUTING A PLURALITY OF QUEUED TASKS I...
- Publication number 20150212738
- Publication date Jul 30, 2015
- Micron Technology, Inc.
- GIUSEPPE D'ELISEO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER TO MANAGE NAND MEMORIES
- Publication number 20140351675
- Publication date Nov 27, 2014
- Federico Tiziani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEAR LEVELING FOR ERASABLE MEMORIES
- Publication number 20140351493
- Publication date Nov 27, 2014
- Massimo Iaculo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUSPENSION OF MEMORY OPERATIONS FOR REDUCED READ LATENCY IN MEMORY...
- Publication number 20120179860
- Publication date Jul 12, 2012
- Francesco Falanga
- G11 - INFORMATION STORAGE
Information Patent Application
VIRTUALIZED ECC NAND
- Publication number 20110307762
- Publication date Dec 15, 2011
- Federico Tiziani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wear Leveling For Erasable Memories
- Publication number 20110271030
- Publication date Nov 3, 2011
- Massimo Iaculo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mass memory device based on a flash memory with multiple buffers
- Publication number 20050021904
- Publication date Jan 27, 2005
- STMicroelectronics S.r.l.
- Massimo Iaculo
- G06 - COMPUTING CALCULATING COUNTING

Antonino Pollio

Person

Patents Grantslast 30 patents

Data separation for garbage collection

Idle mode temperature control for memory systems

Split cache for address mapping data

Dynamic updates to logical-to-physical address translation table bi...

Enhancement for activation and deactivation of memory address regions

Techniques for page line filler data

Initialization techniques for memory devices

Techniques for page line filler data

Data separation for garbage collection

Split cache for address mapping data

Enhancement for activation and deactivation of memory address regions

Initialization techniques for memory devices

Methods and apparatuses for executing a plurality of queued tasks i...

Program progress monitoring in a memory array

Methods and apparatuses for executing a plurality of queued tasks i...

Controller to manage NAND memories

Controller to manage NAND memories

Controller to manage NAND memories

Wear leveling for erasable memories

Controller to execute error correcting code algorithms and manage N...

Wear leveling for erasable memories

Patents Applicationslast 30 patents

IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS

FIRMWARE VERIFICATION USING PARITY INFORMATION

WRITING USER DATA INTO STORAGE MEMORY

DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...

IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS

DYNAMIC UPDATES TO LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION TABLE BI...

TECHNIQUES FOR PAGE LINE FILLER DATA

DATA SEPARATION FOR GARBAGE COLLECTION

SPLIT CACHE FOR ADDRESS MAPPING DATA

SETTING SWITCHING FOR SINGLE-LEVEL CELLS

ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS

TECHNIQUES FOR PAGE LINE FILLER DATA

INITIALIZATION TECHNIQUES FOR MEMORY DEVICES

ENHANCEMENT FOR ACTIVATION AND DEACTIVATION OF MEMORY ADDRESS REGIONS

SPLIT CACHE FOR ADDRESS MAPPING DATA

DATA SEPARATION FOR GARBAGE COLLECTION

PROGRAM PROGESS MONITORING IN A MEMORY ARRAY

METHODS AND APPARATUSES FOR EXECUTING A PLURALITY OF QUEUED TASKS I...

CONTROLLER TO MANAGE NAND MEMORIES

CONTROLLER TO MANAGE NAND MEMORIES

METHODS AND APPARATUSES FOR EXECUTING A PLURALITY OF QUEUED TASKS I...

CONTROLLER TO MANAGE NAND MEMORIES

WEAR LEVELING FOR ERASABLE MEMORIES

SUSPENSION OF MEMORY OPERATIONS FOR REDUCED READ LATENCY IN MEMORY...

VIRTUALIZED ECC NAND

Wear Leveling For Erasable Memories

Mass memory device based on a flash memory with multiple buffers